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June 18, 2026Published
Corporate
Seok-Hee Lee, executive vice president of Intel Foundry
SANTA CLARA, Calif., June 18, 2026 — Intel...
Thursday at 1:38 PM
A correction which I welcome. TechInsight has these numbers but you have to pay.
Thursday at 1:12 PM
S
A leak followed by a "counter-leak"? ;)
Thursday at 1:08 PM
It was a measure of confidence against "variability risk", the "variability" not being stochastics, but process steps, e.g., overlay...
Thursday at 12:22 PM
So it's deceptive to post it as if it shows a usability comparison between high-NA and SALELE low-NA, because it would lead people to...
Thursday at 12:22 PM
One other important consideration for high NA is stitching. I don't think Intel can skirt around it. The High-NA scanner's throughput...
Thursday at 12:21 PM
M
One additional point:
The optical path is not only attached, powered, aligned, cooled, and coupled to function inside the package.
It...
Thursday at 10:19 AM
B
FYI: I was told privately by a trusted source that these numbers are not correct. The correct numbers are under strict NDA which I will...
Thursday at 10:17 AM
B
TSMC notes from SPIE:
High-NA EUV remains challenged in yield as stochastic defect makes high-NA EUV linewidth roughness even harder to...
Thursday at 10:17 AM
B
Intel at SPIE-Feb, from 2024 to 2026, which team is talking, Dev or Prd?
Thursday at 10:16 AM
B
I also note the data is 2-3 years old, in other words before anyone has any experience with trying to actually put high-NA into volume...
Thursday at 10:15 AM
B
Intel says you don't need Double Patterning for 0.55NA 24nm pitch
Thursday at 10:14 AM
B
Indeed -- but my point was that in N2 TSMC *already* have a smaller M0 pitch than single-exposure high-NA can deliver, as you said: "No...
Thursday at 10:14 AM
S
21 nm pitch
Thursday at 10:08 AM
No of course you can't -- all I was saying is that chip pricing matters more at the low end, at the high end you can charge more to...
Thursday at 9:54 AM