Array
(
[content] =>
[params] => Array
(
[0] => /forum/whats-new/latest-activity
)
[addOns] => Array
(
[DL6/MLTP] => 13
[Hampel/TimeZoneDebug] => 1000070
[SV/ChangePostDate] => 2010200
[SemiWiki/Newsletter] => 1000010
[SemiWiki/WPMenu] => 1000010
[SemiWiki/XPressExtend] => 1000010
[ThemeHouse/XLink] => 1000970
[ThemeHouse/XPress] => 1010570
[XF] => 2030871
[XFI] => 1060170
)
[wordpress] => /var/www/html
)
You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please,
join our community today !
JavaScript is disabled. For a better experience, please enable JavaScript in your browser before proceeding.
You are using an out of date browser. It may not display this or other websites correctly.
You should upgrade or use an
alternative browser .
S
the horse said nothing changed
7 minutes ago
Source:
https://www.wsj.com/tech/ai/the-100-billion-megadeal-between-openai-and-nvidia-is-on-ice-aa3025e3
Paywalled article, but I...
25 minutes ago
Actually, Catz was appointed Executive Vice Chairman, and replaced by two co-CEOs, one with direct cloud experience and one with...
Today at 1:03 AM
When she was mouthing in the Trump White House AI honcho meeting, I wondered what was her credential. Sure enough, she got yanked as CEO...
Today at 1:03 AM
K
That's the reality nowadays -- basic pitches that set cell size (M0 and CPP) are almost identical for N3/N2/A16/A14, the gate density...
Today at 1:02 AM
K
Without High NA EUV
Without Dry Photoresist
Without Pattern Sharpening
Only rely on Double / Quad Patterning, we know the story of...
Today at 1:01 AM
K
Stock price update, 5 months later:
Today at 12:50 AM
I don't think what TSMC is doing is quite equivalent to Intel's 14++++ execution. Each + for Intel 14nm actually decreased transistor...
Yesterday at 10:06 PM
I think there is more in this case
+++++++ is Intel Style
But all of those "+" is what is TSMC is doing
N5 > N5++ > N5+++ > N5++++ >...
Yesterday at 10:06 PM
are the number of plus in 14nm correct? I thought there were only 5 plus
Yesterday at 10:06 PM
That's the reality nowadays -- basic pitches that set cell size (M0 and CPP) are almost identical for N3/N2/A16/A14, the gate density...
Yesterday at 10:05 PM
So we don't need Intel, and the US doesn't need semiconductor sovereignty.
All we need is TSMC's US factory.
Yesterday at 10:05 PM
But it's not just about cost, the amount of extra resource -- meaning, engineers! -- needed to support both BSPD and FSPD processes is...
Yesterday at 10:04 PM
I'm sure that with all the conversations Lip-Bu Tan has had with customers he has become aware of the customers who want traditional...
Yesterday at 10:04 PM
That would help, but being more expensive isn't really the biggest issue, it's that for lower-power chips with less dense power grids...
Yesterday at 10:03 PM