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    by Published on 04-20-2014 10:54 PM  Number of Views: 11 
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    There are always a number of other events that are colocated with DAC. One this year is the 23rd International Workshop on Logic and Synthesis (IWLS) that is held the weekend before DAC on May 30th and June 1st. Strictly speaking it is not colocated since it is in the Galleria Park Hotel on Sutter Street a few blocks away whereas DAC itself is in Moscone Center.

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    by Published on 04-20-2014 07:30 PM
    1. Categories:
    2. Semiconductor Manufacturers,
    3. Atmel
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    A few years ago my then-girlfriend was an artist and she had some friends who were in the maker movement, one who ran a tool "lending library" and so on. So she wanted to go to the Maker Faire, which is a huge event held in San Mateo exhibit center. In those days it was more like an outgrowth of burning man but there were already early 3D printers, machine tools and some electronics around. The end of the day had the most amazing ...
    by Published on 04-20-2014 02:00 AM
    1. Categories:
    2. Semiconductor Manufacturers,
    3. Intel
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    This was one of the most memorable keynotes I have seen, absolutely. Probably because it supports my belief that the infamous Intel slide that “projected” Intel will continue a linear manufacturing cost per transistor improvement at 14nm and 10nm is pure marketing fluff. Even more interesting, according to Intel, other semiconductor manufacturers can’t continue ...
    by Published on 04-18-2014 11:54 PM
    1. Categories:
    2. Semiconductor Design,
    3. Mentor,
    4. Events
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    I was at EDPS in Monterey the last couple of days. It is one of the most interesting conferences to attend. Go next year since you already missed it this year. It is not big but the quality of the content is high. Historically the dinner in the middle is in the Monterey Yacht Club and there is a keynote speech. A few years ago it was me but this year there were two upgrades. eSilicon sponsored the dinner so we got some free wine and better food, ...
    by Published on 04-18-2014 09:00 PM
    1. Categories:
    2. Semiconductor Manufacturers,
    3. GlobalFoundries
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    Had I not been briefed personally I may not have believed it. Samsung and GLOBALFOUNDRIES will work closely together on satisfying 14nm wafer demand while sharing Samsung's FinFET secret sauce. This tells me two things: Samsung has more 14nm design wins than I had originally reported and the new GF CEO is serious about the pure play foundry business which I had not reported, ...
    by Published on 04-18-2014 06:11 PM
    1. Categories:
    2. Semiconductor Design,
    3. Docea Power
    content/attachments/10763-docea-power-esl-tool-flow.jpg

    At the recent DVcon there was a keen focus on design verification and validation. Much of the attention is on Logic/circuit design verification, UVM, and IP verification. At the system level functional verification has improved to comprehend complex hardware and software interaction using Virtual Platforms/SystemC and Transaction Level Model simulation that complements the software development and debug activities. The backend validation remains a complex task, which often delays successful product launch and adoption. Designs must ...
    by Published on 04-18-2014 02:30 PM
    1. Categories:
    2. Semiconductor Design,
    3. Cadence
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    The semiconductor design sizes, these days, can easily be of the order of several hundred millions of cells, adding into the complexity of verification. Amid ever growing design sizes, it’s a must that the timing verification is done accurately. Normally Static Timing Analysis (STA) is done to check whether all clocks and signals in the circuit at every stage are properly timed. While introducing ...
    by Published on 04-17-2014 04:30 PM
    1. Categories:
    2. Semiconductor IP,
    3. Arteris
    content/attachments/10769-cisco-common-ioe-platform-architecture.jpg

    In his recent blog on EETimes, Kurt Shuler of Arteris took a whimsical look at the hype surrounding the IoT, questioning the overall absence of practicality and a seemingly misplaced focus on use cases at the expense of a coherent architecture. I don’t think it is all that bleak, but when it comes to architecture, Kurt is right, and here is the case in terms of sensor clusters. ...
    by Published on 04-17-2014 11:00 AM
    1. Categories:
    2. Semiconductor IP,
    3. ARM,
    4. Cadence,
    5. CEVA,
    6. Imagination Technologies
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    I think that the answer is pretty obvious, but the interesting point is to figure out which processor type, and which part of revenues, up-front license or royalties? One of my customers, let’s call him Mr. X, ask me to clarify this point. Mr. X has bought the excellent report from Gartner “Market Share: Semiconductor Design Intellectual Property, Worldwide, 2013” in which most of the IP vendors (at least all the large ...
    by Published on 04-16-2014 02:30 PM
    1. Categories:
    2. Semiconductor Design,
    3. Concept Engineering
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    In EDA arena we often find companies providing customization platforms along with the tools they offer to their customers. I admire such companies because they equip the end users of a tool to extend its functionality as they like according to their environment, thus increasing the designer productivity significantly. And I’m witness to some expert creative users of Cadence tools, during my job at Cadence, who made very powerful customized tools based on the SKILL scripting. What reminded me about ...

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