How do I know when my hardware design is correct and meets all of the specifications? For many years the answer was simple, simulate as much as you can in the time allowed in the schedule and then hope for the best when silicon arrives for testing. There is a complementary method for ensuring that hardware design meets the specifications… Read More
Ravi Subramanian on Trends that are Shaping AI at SynopsysRight before the Synopsys Converge Keynote I caught…Read More
Axiomise Introduces nocProve to Transform NoC Design VerificationAxiomise has recently launched a new verification tool…Read More
Intel Foundry: How They Got Here and Scenarios for ImprovementHow do you get a shortage while not…Read MoreWEBINAR: Reclaiming Clock Margin at 3nm and Below
At 3nm and below, clock networks have quietly become the dominant limiter of SoC power, performance, and yield. Yet most advanced-node designs still rely on abstraction-based signoff methodologies developed when voltage headroom was generous and interconnect effects were secondary.
That assumption no longer holds
As supply… Read More
The First Real RISC-V AI Laptop
At a workshop in Boston on February 27, something subtle but important happened. Developers sat down in front of a RISC-V laptop, installed Fedora, and ran a local large language model. No simulation. No dev board tethered to a monitor. A laptop.
For more than a decade, RISC-V advocates have promised that the open instruction set… Read More
AI-Driven Automation in Semiconductor Design: The Fuse EDA AI Agent
The semiconductor industry is experiencing unprecedented growth in complexity as advanced process nodes, heterogeneous integration, and AI-driven workloads demand increasingly sophisticated chip designs. At the same time, semiconductor companies face rising design costs, increasing engineering workloads, and a shrinking… Read More
TSMC Technology Symposium 2026: Advancing the Future of Semiconductor Innovation
One of my favorite times of the year is coming (sailing season) and my favorite event of the year is coming as the company I most respect will host the best international semiconductor networking event starting here in Silicon Valley.
The 32nd annual TSMC Technology Symposium represents one of the most influential events in the … Read More
Synopsys Explores AI/ML Impact on Mask Synthesis at SPIE 2026
The SPIE Advanced Lithography + Patterning Symposium recently concluded. This is a popular event where leading researchers gather. Challenges such as optical and EUV lithography, patterning technologies, metrology, and process integration for semiconductor manufacturing and adjacent applications are all covered. This… Read More
Unraveling Dose Reduction in Metal Oxide Resists via Post-Exposure Bake Environment
In the realm of extreme ultraviolet (EUV) lithography, metal oxide resists (MORs) have emerged as promising candidates for advanced semiconductor patterning. However, their stability poses challenges, particularly interactions with clean-room environments like humidity and airborne molecular contaminants (AMCs) … Read More
CEO Interview with Dr. Mohammad Rastegari of Elastix.AI
Mohammad Rastegari is a prominent AI researcher and entrepreneur currently serving as the CEO and Co-Founder of Elastix.AI. Based in the Greater Seattle Area, he also holds the position of Affiliate Assistant Professor at the University of Washington’s Electrical & Computer Engineering Department. His professional… Read More
Tesla and Samsung Relationship Update
The majority of my 40+ year career has been spent managing the relationship between leading-edge semiconductor design and manufacture, working with just about every commercial foundry and top customer in one way or another. It’s my thing—it fascinates me. I’m also a fan of disruption, and the latest disruptions the semiconductor… Read More
Podcast EP335: The Far Reaching Impact of UCIe with Dr. Debendra Das Sharma
Daniel is joined by Dr. Debendra Das Sharma, a Senior Fellow and Chief I/O architect in the Data Platforms and Artificial Intelligence Group at Intel. He is a member of the National Academy of Engineering (NAE), Fellow of IEEE, and Fellow of International Academy of AI Sciences. He is a leading expert on I/O subsystem and interface… Read More



Tesla and Samsung Relationship Update