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QED (Quick Error Detection) can be a powerful complementary addition to verification but can be subject to size constraints. This month’s paper looks at a fix for that limitation. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A)… Read More
For the past decade, the semiconductor industry has been moving in one direction: shift-left, specifically, shifting more validation into the pre-silicon phase. The idea was straightforward: if software ultimately determines how a system behaves, then software should become a primary vehicle for verification.
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Intel 18A vs Intel 18A-P: What Is the Difference and Why Does It Matter?