Array
(
[content] =>
[params] => Array
(
[0] => /forum/whats-new/latest-activity?before_id=114268
)
[addOns] => Array
(
[DL6/MLTP] => 13
[Hampel/TimeZoneDebug] => 1000070
[SV/ChangePostDate] => 2010200
[SemiWiki/EmailDomainReplace] => 1000010
[SemiWiki/Newsletter] => 1000010
[SemiWiki/WPMenu] => 1000010
[SemiWiki/XPressExtend] => 1000010
[ThemeHouse/XLink] => 1000970
[ThemeHouse/XPress] => 1010570
[XF] => 2031070
[XFI] => 1060170
)
[wordpress] => /var/www/html
)
You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please,
join our community today !
JavaScript is disabled. For a better experience, please enable JavaScript in your browser before proceeding.
You are using an out of date browser. It may not display this or other websites correctly.
You should upgrade or use an
alternative browser .
I
Who's right then -- Intel or Fred? ;-)
Thursday at 5:42 AM
S
Intel says you don't need Double Patterning for 0.55NA 24nm pitch
Thursday at 5:23 AM
S
M0 for N3E is 23nm
Thursday at 4:53 AM
I
Indeed, this must have gone thru TSMC's thinking, perhaps Samsung too?
Thursday at 4:25 AM
F
Indeed, this must have gone thru TSMC's thinking, perhaps Samsung too?
Thursday at 4:23 AM
F
Indeed -- but my point was that in N2 TSMC *already* have a smaller M0 pitch than single-exposure high-NA can deliver, as you said: "No...
Thursday at 4:21 AM
I
Indeed -- but my point was that in N2 TSMC *already* have a smaller M0 pitch than single-exposure high-NA can deliver, as you said: "No...
Thursday at 4:14 AM
F
I recall TSMC already had 28 nm pitch M0 for N5P.
Thursday at 3:58 AM
I
Surely the biggest issue with TSMC adopting high-NA is not just the economics/throughput, but the sheer number of machines that would be...
Thursday at 3:21 AM
I
M0 pitch in TSMC N2 is less than 24nm... ;-)
Thursday at 3:14 AM
S
28 nm pitch was hinted at in an SPIE paper last year.
There's no advantage for increasing NA from 0.33 to 0.55 for a 28 nm pitch. The...
Thursday at 2:39 AM
An offhand disclosure by Intel's CFO about surging demand for its advanced packaging business inadvertently revealed the scale of a...
Thursday at 1:20 AM
B
Fake supply issues.
You have to believe these guys are loving these numbers.
They have ZERO incentive to address "supply issues"
Wednesday at 11:56 PM
B
Micron guided FQ3 GM to 81%!
At those GM levels, it makes zero sense for the suppliers to let supply catch up with demand as that would...
Wednesday at 11:55 PM
C
BTW, found few other media link talking about HNA delivered in 2024. enjoy it...
Wednesday at 10:26 PM