Array
(
[content] =>
[params] => Array
(
[0] => /forum/whats-new/latest-activity?before_id=110381
)
[addOns] => Array
(
[DL6/MLTP] => 13
[Hampel/TimeZoneDebug] => 1000070
[SV/ChangePostDate] => 2010200
[SemiWiki/Newsletter] => 1000010
[SemiWiki/WPMenu] => 1000010
[SemiWiki/XPressExtend] => 1000010
[ThemeHouse/XLink] => 1000970
[ThemeHouse/XPress] => 1010570
[XF] => 2031070
[XFI] => 1060170
)
[wordpress] => /var/www/html
)
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Most 'easy digest' (i.e. not expert) news sites use a 3X number, but Applied Materials says "roughly 2X". I'm assuming 3X may not be...
Apr 6, 2026
S
I guess DMR would help load that alongside Wild Cat Lake just my thought Intel shouldn't use Advanced Packing on Cheap stuff like...
Apr 6, 2026
S
I worked closely with Pat on and off for years. He seemed mostly optimistic about himself and his strategies. I think other Intel...
Apr 6, 2026
S
I have met Pat before. He is probably the most optimistic executive I worked with at Intel (Many years ago). I like that trait.... just...
Apr 6, 2026
M
I have met Pat before. He is probably the most optimistic executive I worked with at Intel (Many years ago). I like that trait.... just...
Apr 6, 2026
M
Actually we have a cost model for the final product. We have a model for TSM prices, die size, yield etc.
IFS sells wafers to Intel...
Apr 6, 2026
M
Look at the die size for HBM vs DDR chips. The die size penalty is not small. Its not 3x either.
Apr 6, 2026
M
your source is a little dated. Samsung is not number three in HBM anymore.
Luckily DDR5 has higher margins for Micron
Apr 6, 2026
M
Isnt the objective of business to get max pricing for their product?
Restrict supply to push prices , if no alternative supplier , isnt...
Apr 6, 2026
F
Yes, the HBM TSVs have a keep-out-zone which will still take up a "small" % of the area.
Apr 6, 2026
C
Feel like Intel people dont know the fundamentals well enough and yet try to resolve something impossible?
Apr 6, 2026
F
Fred, fwiw - The existing capacity has technically been technically been "reduced" as the makers have converted from DRAM to HBM. You...
Apr 6, 2026
F
36 nm pitch has significant stochastic defectivity, which has been reported by Samsung and others (first by IMEC).
Samsung also...
Apr 6, 2026
S
18A minimum pitch is 36nm, a relatively "easy" pitch for EUV, and which the industry already also has experience with. So I don't see...
Apr 6, 2026
Fred, fwiw - The existing capacity has technically been technically been "reduced" as the makers have converted from DRAM to HBM. You...
Apr 6, 2026
Xebec replied to the thread Samsung and SK are expanding fast, but why is memory still in short supply?.Most 'easy digest' (i.e. not expert) news sites use a 3X number, but Applied Materials says "roughly 2X". I'm assuming 3X may not be...
Like.
I worked closely with Pat on and off for years. He seemed mostly optimistic about himself and his strategies. I think other Intel...