Array
(
[content] =>
[params] => Array
(
[0] => /forum/whats-new/latest-activity?before_id=106350
)
[addOns] => Array
(
[DL6/MLTP] => 13
[Hampel/TimeZoneDebug] => 1000070
[SV/ChangePostDate] => 2010200
[SemiWiki/Newsletter] => 1000010
[SemiWiki/WPMenu] => 1000010
[SemiWiki/XPressExtend] => 1000010
[ThemeHouse/XLink] => 1000970
[ThemeHouse/XPress] => 1010570
[XF] => 2030871
[XFI] => 1060170
)
[wordpress] => /var/www/html
)
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C
That's the reality nowadays -- basic pitches that set cell size (M0 and CPP) are almost identical for N3/N2/A16/A14, the gate density...
Friday at 6:42 AM
That's the reality nowadays -- basic pitches that set cell size (M0 and CPP) are almost identical for N3/N2/A16/A14, the gate density...
Friday at 6:27 AM
During the last year many discussions on this SemiWiki website centered on the reasons why Intel started struggling versus the success...
Friday at 6:23 AM
That's the reality nowadays -- basic pitches that set cell size (M0 and CPP) are almost identical for N3/N2/A16/A14, the gate density...
Friday at 3:41 AM
Without High NA EUV
Without Dry Photoresist
Without Pattern Sharpening
Only rely on Double / Quad Patterning, we know the story of...
Friday at 3:40 AM
we went through this 5 years ago with the rumors. Lets see when we get commits, tapeouts and Wafers.
And again, the issue isnt only...
Friday at 3:21 AM
D
I have worked with multiple factories in Singapore. US can get within 5% on Fab wafer cost (Singapore can be expensive on many items)...
Friday at 2:22 AM
D
You mean add another not-really-big-enough-volume (and late to market!) process to the one they're already got -- plus you need...
Friday at 1:52 AM
D
It's not that simple, the metal stack and processing and qualification and DK and extraction and layout and libraries and SRAMs and...
Friday at 1:49 AM
I
That's the reality nowadays -- basic pitches that set cell size (M0 and CPP) are almost identical for N3/N2/A16/A14, the gate density...
Friday at 1:46 AM
D
Depends what you mean by "most customers"... ;-)
TSMC have said the BSPD (A16 process as opposed to N2) is suitable for HPC chips with...
Friday at 1:44 AM
E
I don't know where you get 18A being a competitor to N2 from -- 18A competes with N3, 14A competes with A16 which is the BSPD version of...
Friday at 12:56 AM
E
Like boy scouts, being prepared is one thing, but whether you actually have the resources is another thing entirely. No amount of...
Friday at 12:54 AM
E
And the market's reaction to Microsoft's comments today:
Friday at 12:49 AM
E
It's interesting that it's like a U-curve for hardware -- the (late) 1970s and 1980s had a LOT of custom silicon, 1990s saw...
Friday at 12:49 AM
Like.
That's the reality nowadays -- basic pitches that set cell size (M0 and CPP) are almost identical for N3/N2/A16/A14, the gate density...
hist78 reacted to IanD's post in the thread Intel Foundry is way behind TSMC, but the goal is #2 by 2030 with
user nl posted the thread Running a foundry of Cash Cows and Little Fish: TSMC and the role of chiplets in SemiWiki Main Forum ( Ask the Experts! ).During the last year many discussions on this SemiWiki website centered on the reasons why Intel started struggling versus the success...
Xebec reacted to IanD's post in the thread Intel Foundry is way behind TSMC, but the goal is #2 by 2030 with
kvas reacted to MKWVentures's post in the thread Intel Secures TSMC Overflow Orders, Challenging Samsung Foundry with
Haha.
And the market's reaction to Microsoft's comments today: