Depends on how you mean. Assuming that we are talking revenue, and we aren't talking about maybe Intel consistently out-executing TSMC for the next 20-30 years. Then TSMC needs to have at least 3 10 nanometers in a row. The most recent 2 TSMC nodes have for the past little while have been around half of TSMC's revenue. So Intel needs to win 100% of 2 nodes in a row to be around the size of TSMC. But if we are talking technology as long as TSMC and Intel's roadmaps hold, the current roadmap from TSMC looks weak to me (3 years between full nodes versus Intel's 2 years with the Intel half nodes being bigger steps and the TSMC full nodes being similar sized steps). 18A is more advanced than N2 in some ways, N2 is more advanced than 18A in some ways. The wind seems to be blowing towards N2 being on average better. Foundry products come around a similar time frame, and Intel 18A products lead Apple N2 by about a year. 14A is easily lining up to be better than N2, and if Intel is serious about 2 year cadence, we are talking internal products beating first A14 products to market by 2 years and intel foundry 14A products should lead by around 1 year. Then by the time Apple launches their A14 chips and starts A14 production for everyone who isn't Apple, we should be seeing 10A Intel chips and 10A foundry production start. Even if we assume TSMC is sandbagging by 5% on all of the numbers TSMC showed for A14, I just cannot comprehend how that could be competitive with whatever Intel has for 10A unless 10A is the biggest nothingburger of a node in semiconductor history. Intel even has the advantage of their BSPDN application, allowing them to be 1-2 nodes behind TSMC on litho scaling while maintaining the same density.Intel needs TSMC to have a 10nm moment to win
While we are now getting waaaaaaaaaaay into too far out for anyone to really known anything, but just for fun (and also to illustrate just how bad a 3 year cadence looks to me). I know Dan Hutcheson believes that from the research progress he has seen and Intel's demonstrated process development capabilities that he thinks Intel will be first to CFETs sometime during the 1st half of the 2030s. For their part IMEC believes CFET will be around A7 generation in 2031. If that is what bears out, then Intel 7A CFET products on shelves with foundry customers starting first wafers 6 years after 18A in 2031 versus A14P/A14P+BSPDN products on shelves and A10 forksheets only just entering production. Now FWIW, I don't think TSMC will just completely roll over. But without working on more processes in parallel, or having each full node be a big enough improvement to overcome the slower cadence, it is not possible to maintain process leadership. I feel like TSMC has to have something big so Intel doesn't just gradually open up another multi-year process lead. We just don't know what it is at the moment. In a sense, this is the same dilemma the industry encountered when process complexity was increasing exponentially in the heavy multipatterning era. Intel chose to extend development times but have more aggressive shrinks to compensate. On paper the CAGR was greater than what TSMC was doing, but it was too hard to execute and Intel fell behind. TSMC responded with keeping doing more modest process node definitions with gaps not to exceed 2 years starting with 16FF->10FF until the 3 year gap between N5->N3 (and with 10FF/N7 they even had a 1 year gap between process nodes).