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TSMC Discloses N2 Defect Density Lower Than N3 At The Same Stage Of Development

As TSMC did not specified, I remember TSMC N3B was reported to be having "serious" issues


also rumor that Apple was paying only usable die not the whole wafer.

With such a low target, it is not surprise that they can beat it and it is really not mean that much.

That just bring my calculation above making more sense, i.e. N2 is not production ready for a larger chip such as EYPC compute i.e. 50 - 80 mm^2 range, it could be the same 55 - 70% yield if they go ahead. AMD will then only pay for good die not the whole wafer. I also explain why Apple do not jump into N2 right away.

They are not ready !!!!

Apple had a problem with their version of N3 and there was a delay. I believe it was an EUV issue, TSMC reduced the amount of layers to resolve it and better optimize N3. This will not be the case with N2. Several companies have already taped out including Apple and AMD. TSMC does make mistakes but they learn from them. I can assure you Apple does not pay for good die. Stupid rumor.
 
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