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The three major memory powerhouses are investing in 1c DRAM, targeting the AI and HBM markets

F

Fred Chen

Moderator
Major memory companies are accelerating their investments in 1c (6th-generation 10nm-class) DRAM. Samsung Electronics has already begun building mass production lines since the first half of this year, and SK Hynix is reportedly discussing specific plans for its recent conversion investment. Micron also received subsidies from the Japanese government this month for its new 1c DRAM facility.

According to industry sources on the 21st, major memory companies are focusing on new and conversion investments for mass production of 1c DRAM.

1c DRAM is a next-generation DRAM that major memory companies are aiming to mass produce in the second half of this year. Samsung Electronics has decided to proactively adopt 1c DRAM in its HBM4 (6th-generation high-bandwidth memory). SK Hynix and Micron plan to utilize 1c DRAM in general-purpose DRAM, including servers.

Samsung Electronics is most aggressively expanding its 1c DRAM production capacity. It is currently building a new 1c DRAM mass production line at its Pyeongtaek Campus 4 (P4) and is also pursuing investments in converting its Hwaseong Line 17 to 1c DRAM. The production capacity it will secure by the end of the year is estimated to reach a maximum of 60,000 wafers per month.

SK Hynix announced in its Q2 2025 earnings announcement in July that "the conversion investment for 1c DRAM will begin in the second half of this year and will be fully implemented next year," and that "we are currently establishing a management plan and will share the specific plan once it is finalized."

According to industry sources, the conversion investment is likely to take place at the M14 fab in Icheon. M14 is a fab that has been repurposing some of its existing NAND lines for DRAM mass production. SK Hynix is currently discussing plans to remove the older DRAM facilities there and introduce a 1c DRAM line.

A semiconductor industry insider explained, "The 1c process can be used not only for high value-added DRAM for servers, but also for HBM4E (7th generation HBM), so it is an area that SK Hynix is paying attention to," and "Although facility investment has not been confirmed yet, we expect active investment to be made in all areas of the process next year."

https://zdnet.co.kr/view/?no=20250919154604
 
1c uses EUV as well:

AI overview:
  • SK hynix:
    This company is a leader in EUV adoption for DRAM, utilizing five or more EUV layers for its 1c DRAM and increasing its utilization as the process has advanced from earlier generations.

  • Micron:
    Also uses EUV for its equivalent 1γ DRAM to achieve high bit density and performance.

  • Samsung:
    While initially more aggressive with EUV, it has also been incorporating EUV into its 1c DRAM production, though reports suggest a reduction in EUV layer count compared to earlier plans.
 
benb said:
1c uses EUV as well:

AI overview:
  • SK hynix:
    This company is a leader in EUV adoption for DRAM, utilizing five or more EUV layers for its 1c DRAM and increasing its utilization as the process has advanced from earlier generations.

  • Micron:
    Also uses EUV for its equivalent 1γ DRAM to achieve high bit density and performance.

  • Samsung:
    While initially more aggressive with EUV, it has also been incorporating EUV into its 1c DRAM production, though reports suggest a reduction in EUV layer count compared to earlier plans.
Click to expand...
The three companies have taken different paths, not just in EUV deployment. The shrink from 1a to 1b (14nm to 12nm) is larger than from 1b to 1c (12nm to 11nm). So the EUV is not a big help in this regard.
 
Xebec said:
3D DRAM is next ?
Click to expand...
The thinning of the dielectric between bit line and storage node contact results in rapidly growing parasitic capacitances and leakage. So this is the problem with current planar 6F2 DRAM. 4F2 DRAM offers a way out but capacitor patterning is still a problem and more than one stacked layer is still preferred. So monolithic 3D DRAM with many stacked layers (like 3D NAND) is the remaining option. Not sure if HBM can go 100 dies high!
 
Last edited:
3D DRAM does not require EUV:

AI Overview

No, 3D DRAM does not inherently require EUV lithography; in fact, the vertical stacking of cells in 3D DRAM allows for the use of older Deep Ultraviolet (DUV) lithography, such as ArF, which can result in lower production costs compared to EUV-dependent planar DRAM, according to reports from May 2025. While EUV is being adopted for advanced planar DRAM, 3D DRAM's architecture circumvents the need for the most advanced and costly EUV tools.

EUV litho may be a stranded asset in DRAM space. And the China competition may be intense.
 
DRAM really is in difficult situation. Some companies are planning 1d or 1e DRAM (but since their 1c is already in 11nm class, improvement will be minimal) while developing 0a DRAM with vertical channel(gate and capacitor are stacked together) scheme. After vertical channel, they need to mass produce 3D DRAM(storage units are stacked in single wafer) to continue density improvement(not really 'scaling' in this case). DRAM companies might not breakeven, even if they reach 100 stacks of DRAM unit storages(5 stacks so far).
 
benb said:
3D DRAM does not require EUV:

AI Overview

No, 3D DRAM does not inherently require EUV lithography; in fact, the vertical stacking of cells in 3D DRAM allows for the use of older Deep Ultraviolet (DUV) lithography, such as ArF, which can result in lower production costs compared to EUV-dependent planar DRAM, according to reports from May 2025. While EUV is being adopted for advanced planar DRAM, 3D DRAM's architecture circumvents the need for the most advanced and costly EUV tools.

EUV litho may be a stranded asset in DRAM space. And the China competition may be intense.
Click to expand...
Main issue right now is they can't get enough layers (>100).
 
semiman said:
DRAM really is in difficult situation. Some companies are planning 1d or 1e DRAM (but since their 1c is already in 11nm class, improvement will be minimal) while developing 0a DRAM with vertical channel(gate and capacitor are stacked together) scheme. After vertical channel, they need to mass produce 3D DRAM(storage units are stacked in single wafer) to continue density improvement(not really 'scaling' in this case). DRAM companies might not breakeven, even if they reach 100 stacks of DRAM unit storages(5 stacks so far).
Click to expand...
The 4F2 vertical channel scheme is still continued scaling of bit line pitch (which increases its capacitance relative to capacitor) but the slanted active area pattern is gone, and the buried word line now becomes a side word line. It is projected to only be used for three years (three nodes) before 3D DRAM.
 
Fred Chen said:
The 4F2 vertical channel scheme is still continued scaling of bit line pitch (which increases its capacitance relative to capacitor) but the slanted active area pattern is gone, and the buried word line now becomes a side word line. It is projected to only be used for three years (three nodes) before 3D DRAM.
Click to expand...
4F2 might last longer than 3 gens thanks to slow progress of 3D DRAM pathfinding. BTW does side-wordline mean 'WL wrapped around channel'?
 
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