Taiwan's No. 2 chipmaker UMC eyes entering cutting-edge race

[osnium]

Yes, Tower is going to use Intel's 300mm capable fab space in New Mexico, tool it with equipment worth up to $300 mil and fab 65nm chips.


Intel gets Intel 6 as foundry offering with foundry grade PDKs, IPs and libraries (& to use Intel 7 based fully depreciated equipments and older fab capacity) and UMC gets another finfet tech node, US footprint and readily available fab space. Looks like Win-Win for both.

Intel has been using TSMC's N6 node for IO & Platform control tiles on Client CPUs. Maybe they find use on those lines for other customers. UMC\Intel 12 was announced in 1Q'24 and will be HVM in 1Q'27. So this UMC\Intel 6 will likely be roughly ~2028.

Do you expect this UMC 6nm node process to use EUV? Intel 7 does not use EUV as per IEDM papers and so if it uses EUV, it will be a brand new node. It would also mean that it would run either in Ireland or Arizona.

 

[Paul2]

Do you expect this UMC 6nm node process to use EUV? Intel 7 does not use EUV as per IEDM papers and so if it uses EUV, it will be a brand new node. It would also mean that it would run either in Ireland or Arizona.

UMC can just rent Intel's fab, with equipment and send their own engineers with their own recipes to cook chips using their own nodes.

 

[MKWVentures]

If the partner with Intel on this, it is a great solution for both companies. Intel given leading edge capability to UMC or GF is a great idea

they can just rebrand Intel wafers.

 

[Paul2]

If the partner with Intel on this, it is a great solution for both companies. Intel given leading edge capability to UMC or GF is a great idea

they can just rebrand Intel wafers.

Another moment here: UMC clients will have much smaller dies, and they are less skittish about throwing dies out. No need for too much bare die testing, and repair capacity. And if anyone will need it, these buyers will likely go for OSAT, and not UMC's own packaging offer anyway.

With ASICs, you usually don't have that much binning opportunity, it's either performs enough for the task it's made for, or it doesn't.

Something like NIC chips may have fair sized SRAM blocks, but the extra testing, fuzing, routing circuitry, and above all spare SRAM blocks might not be that cheap both area, and process-wise than just using that to make more dies.

Dumbed down test/repair/binning may actually give more chips per acre, and drive up yield.

This is also the reason that the general preference in the budget ICs space is learning how to make well performing ASICs with as little SRAM as possible.