lispwright
Member
As I, very much not a fab guy, understand it, Intel's 10 nm was very roughly equivalent to TSMC's N7 in what it targeted, but a bit more aggressive.2) the 10nm fiasco was blamed on EUV, but that wasnt the major issue or the main reason for 10nm delay (which is best described as a disaster, followed by a failed rescue, followed by another failed rescue)
I strongly suspect Intel's legendary high level bad management not only seeped down to its crown jewel of fab technology, but was responsible for those multiple failed rescues. Did the company even internally acknowledge it was a failure until the single SKU Cannon Lake launch, with i's biggest piece of silicon, the iGPU fused off, with essentially no laptops using it for sale? BK was purged from Intel three months later.
So neither company planned on using EUV for their first iteration of this general node, but TSMC's success allowed it to ease into EUV use with N7+ for "up to four of its critical layers." This was not much of an option for Intel until the base node worked well enough (and even then, there was a terrible mistake made with a clock tree circuit for Intel 7+ higher end Raptor Lake SKUs).
