semiwiki.com
I should hope I was right, what I said was based on actual PDK and layouts, not TSMC (or any other) website... ;-)
Are you absolutely sure about N6? As I said we never used it, but I'm pretty sure it was a linear shrink and cost reduction of N7, not N7P -- because the way the layout rules work for quad DUV and EUV patterning are different (end cut rules etc) which is why N7P was incompatible with N7 and hardly anyone used it (including us) because IP needed a total relayout.
If you think N3 was bad for EUV layers (and wafer prices!), you shouldn't even look at N2... ;-)
i was seeing rumors that N3 and N2 had the same EUV layers count and those seemed false thanks for the confirmation
as for N2 expense only time will tell i guess.
OK, my first speculation was wrong then (but my second one wasn't!) -- note the comment about backward-compatible design rules which was what killed N7P, so TSMC learned their lesson then... ;-)Yes I am sure. Would you dare to question Scotten Jones?
From TSMC:
EUV process improves logic density; provides backward compatibility
Extreme ultra-violet (EUV) lithography requires fewer masking layers and offers better process variation control. The 6nm (N6) technology utilizes additional EUV layers to improve process simplicity, shorter cycle times, and improve productivity. N6 provides improvements in power, performance, and density over N7 with similar defect density thanks to a smaller standard cell library. Through lithography process optimization, optical proximity correction (OPC), and etch co-optimization, N6 provides backward-compatible design rules, device models, and IP as N7, making the migration from N7 to N6 very straightforward. It also shares the same design flow and EDA tool availability.
they already have revenue, Operating income. the only thing missing is sharing details of the OM. Which they obviously have in order to report the OM.
There's some more on the differences among the N7 processes here: https://www.eettaiwan.com/20200115nt61-7nm-comparision/ although N6 was not out yet it seems. But there's actually an N7P different from N7+.
IIRC N7 DUV process used 4P4E while N7+/N6 used 1P1E. But it's a big misunderstanding to equalize the cost and yield of DUV 1P1E and EUV 1P1E.Yes I am sure. Would you dare to question Scotten Jones?
From TSMC:
EUV process improves logic density; provides backward compatibility
Extreme ultra-violet (EUV) lithography requires fewer masking layers and offers better process variation control. The 6nm (N6) technology utilizes additional EUV layers to improve process simplicity, shorter cycle times, and improve productivity. N6 provides improvements in power, performance, and density over N7 with similar defect density thanks to a smaller standard cell library. Through lithography process optimization, optical proximity correction (OPC), and etch co-optimization, N6 provides backward-compatible design rules, device models, and IP as N7, making the migration from N7 to N6 very straightforward. It also shares the same design flow and EDA tool availability.
Indeed -- but the other key point is how many layers EUV is used on, and in newer processes how many separate EUV masks are used (multipatterning).
Just like "5nm" and "4nm" and "3nm" and "2nm" then... ;-)TSMC N6 and TSMC N5 came out at the same time (Q1 2020). TSMC considers N7, N7+ and N6 one node, that is how they report it. Same with TSMC N5 and N4. TSMC N3 and N2 will be reported separately. So TSMC N7 was the first EUV node, N5 2nd, N3 3rd and N2 4th. This is all marketing stuff so it does not need to make sense.
Yes, but it's still fictional isn't it?
yes but it's not referring to nm
Yeah but good luck explaining that many numbers to people and not to mention TSMC/Samsung/Intels node names are so bad already. At least no one named their process AI12 Process
It might not say "nm" any more but that's what most non-techie people *think* it means -- and as for Intel's "18A", don't get me started... :-(yes but it's not referring to nm
Yeah but good luck explaining that many numbers to people and not to mention TSMC/Samsung/Intels node names are so bad already. At least no one named their process AI12 Process
I was looking over some of Intel's recent SPIE papers from within the past year. ASML/Zeiss can't measure the High-NA EUV system aberrations at their own site (too big), they have to do so at the customer site. That means all High-NA systems are basically shipped out of spec, and one or more mirrors need to be replaced before final acceptance. This may even need more than one iteration! Can't really use this as an anchor for process release schedule...
Chipzilla bets the farm on 14A while chasing TSMC
Troubled Chipzilla is doubling down on ASML’s obscenely expensive High-NA EUV lithography kit, ordering two more of the €350 million-plus contraptions in the hope of dragging its much-hyped 14A process over the line.
Intel has one of the machines installed and is parading 14A as the historic moment it finally ships a leading-edge node on time. Given Chipzilla’s history of slipping roadmaps, renaming old nodes, and generally disappointing investors, most of the industry is taking that claim with a shovel of salt.
The High-NA toys are crucial to Intel’s so-called IDM 2.0 strategy, which is supposed to claw back ground lost to TSMC and Samsung. Without them, the 14A node risks being dead on arrival.
For ASML, it’s all gravy. Intel hoovered up every available High-NA slot in 2024 and is now poised to become the biggest customer for the kit worldwide. Each machine is a warehouse-sized monstrosity of lenses, mirrors and Dutch engineering, and ASML can’t build them fast enough. Every sale is a license to print money.
Chipzilla insists it is on track to get 14A into production and shipping before TSMC can ramp its equivalent nodes, but sceptics point out that Intel has promised this sort of comeback before and ended up years behind. Even if the machinery works flawlessly, ramping yields to competitive levels is another headache entirely.
Intel splashes more cash on ASML’s magic machines
Chipzilla bets the farm on 14A while chasing TSMC Troubled Chipzilla is doubling down on ASML’s obscenely expensive High-NA EUV lithography kit, ordering two more of the €350 million-plus contraptions in the hope of dragging its much-hyped 14A process over the line. Intel has one of the machines...www.fudzilla.com
