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Intel and SoftBank, through their subsidiary Saimemory, have been developing an alternative technology to the popular high-bandwidth memory (HBM) to provide more bandwidth and capacity for memory modules used with powerful AI accelerators. At VLSI 2026 in June, Saimemory is scheduled to present a paper on the newly developed HB3DM memory, which is based on Z-Angle Memory (ZAM) technology. This name refers to the vertical (Z-axis) stacking of dies, similar to traditional HBM. However, Intel aims to achieve impressive results using state-of-the-art manufacturing technology. The first generation of HB3DM will feature a total of nine layers, stacked using a hybrid bonding technique for 3D chip placement. At the base will be a logic layer that manages data movement within the chip, with eight DRAM layers on top for data storage. Each layer will include about 13,700 TSVs for hybrid bonding.
Intel and SoftBank, through their subsidiary Saimemory, have been developing an alternative technology to the popular high-bandwidth memory (HBM) to provide more bandwidth and capacity for memory modules used with powerful AI accelerators. At VLSI 2026 in June, Saimemory is scheduled to present...
Intel and SoftBank, through their subsidiary Saimemory, have been developing an alternative technology to the popular high-bandwidth memory (HBM) to provide more bandwidth and capacity for memory modules used with powerful AI accelerators. At VLSI 2026 in June, Saimemory is scheduled to present...
I think Intel is just responsible for the stacking part. The DRAM is from PSMC apparently. The logic base die, if it had been made on Intel 18A or Intel 3, I'm sure that would have been called out.
Fred, can you please cite your source? I don't think ZAM is "still vertically stacked DRAM". There is a "vertical" component, but why is it called "Z-Angle" if it's not that different from HBM?
I thought ZAM had the HBM stack rotated 90 degrees and somehow bonded along the edge (saw some patents on this). But the figures in the article don't show this. Confusing.
I’ve lost track of how many times Intel has entered and exited the memory business, whether through manufacturing, joint ventures, partnerships, development, specification/standard setting, or licensing. So I asked my unpaid assistant Mr. Claude to find out.
Here's the full list:
Intel Memory History - Entries, Exits & Partnerships
Summary: 6 entries · 7 exits · 6 JVs/partnerships · 2 licensing/spin-outs across 57 years
Era 1 — DRAM & SRAM (Founded on Memory)
1968 — ENTRY: Intel founded on SRAM/DRAM chips; 1103 DRAM displaced magnetic core memory as industry standard
1971 — ENTRY: EPROM/ROM business launched; Intel invented the EPROM
1985 — EXIT: Exited DRAM & SRAM manufacturing; Japanese competitors destroyed margins; pivoted to microprocessors
Era 2 — NOR Flash (1988–2010)
1988 — ENTRY: Launched world's first NOR flash chip, replacing EPROM for firmware/boot code storage
2008 — SPIN-OUT: NOR flash assets spun into Numonyx JV with STMicroelectronics (Intel 45.1%, ST 48.6%, Francisco Partners 6.3%); ~2,500 employees transferred; ~$300M impairment charge
2010 — EXIT: Numonyx sold to Micron for $1.27B; Intel exited NOR flash entirely
Era 3 — Rambus RDRAM (1996–2003)
1996–97 — PARTNERSHIP: Intel signed exclusive development & license agreement with Rambus; committed all chipsets (i820, i840, i850, i860) to RDRAM; agreement secretly barred Intel from shipping DDR chipsets until 2003
2001–03 — EXIT: Abandoned RDRAM after it proved too expensive, hot, and high-latency; DDR matched RDRAM performance at far lower cost; Intel quietly launched i865/i875 DDR chipsets in 2003, ceding years of market leadership to AMD
Era 4 — NAND Flash (2005–2022)
2005–06 — JV: Formed IM Flash Technologies (IMFT) with Micron (Intel 49%, Micron 51%); each contributed ~$1.2B; fabs in Lehi UT, Manassas VA, Boise ID; Apple pre-paid $250M to each partner
2007 — JV EXPANSION: Formed IM Flash Singapore (IMFS); opened April 2011; pioneered 34nm then 20nm NAND
2018–19 — EXIT FROM JV: Micron exercised call option in Oct 2018; deal closed Jan 2019; Intel retained standalone Dalian NAND fab and SSD business
2020–25 — FULL EXIT: Sold NAND + SSD business to SK Hynix for ~$8.85B in two parts (Phase 1: $7B Dec 2021 — Dalian fab + IP; Phase 2: $1.9B Mar 2025 — remaining IP + employees); rebranded as Solidigm
Era 5 — 3D XPoint / Optane (2012–2022)
2012–15 — JV: Jointly developed 3D XPoint with Micron using IMFT Lehi fab; announced July 2015 as 1000× faster than NAND
I’ve lost track of how many times Intel has entered and exited the memory business, whether through manufacturing, joint ventures, partnerships, development, specification/standard setting, or licensing. So I asked my unpaid assistant Mr. Claude to find out.
Fred, can you please cite your source? I don't think ZAM is "still vertically stacked DRAM". There is a "vertical" component, but why is it called "Z-Angle" if it's not that different from HBM?
I thought ZAM had the HBM stack rotated 90 degrees and somehow bonded along the edge (saw some patents on this). But the figures in the article don't show this. Confusing.
Yes, I agree, I probably saw the same figures. So I think this paper is not about Z-Angle Memory. HB3DM is just something else they are trying. ZAM might still be under development. It is not mentioned in the abstract at all. TechPowerUp jumped the conclusion.
