May 20, 2026
Intel Foundry has reached a notable systems foundry milestone with the demonstration of the world’s thinnest gallium nitride (GaN) chiplet, measuring just 19 micrometers. This research achievement highlights Intel Foundry’s ability to integrate compound semiconductors, advanced silicon process technology, and advanced packaging to address the increasing power and performance demands of AI and high-performance computing systems. By tightly integrating GaN power devices with silicon‑based digital control, this approach enables higher power density, improved efficiency, and more compact system designs, giving customers greater flexibility as they build heterogeneous, next-generation platforms. The breakthrough underscores Intel Foundry’s systems foundry strategy—bringing together process, packaging, and ecosystem innovation to support scalable performance and power efficiency for the AI era.
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The introduction of TSVs to our Embedded Multi-die Interconnect Bridge (EMIB) technology is driving increased performance for large package architectures. EMIB-M and EMIB-T are explained in a short video highlighting these industry-leading technologies. See how EMIB-T delivers superior power efficiency and bandwidth for demanding applications.
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As AI models grow larger and more power‑hungry, performance gains hinge less on transistor scaling and more on how chips are assembled. In Wired, industry leaders explain why advanced packaging—linking compute, memory, and accelerators at scale—has become a critical bottleneck and strategic differentiator shaping the future of AI infrastructure.
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Fresh from GOMACTech 2026, Tao Zhou, Senior Principal Engineer at Intel, shares how Intel Foundry and partners are executing on secure, onshore microelectronics for defense. He highlights interoperable chiplets, advanced packaging, and system-level enablement, plus technical contributions across architecture, design sign-off reliability, and Intel 18A device innovations aimed at AI-ready, mission-critical systems.
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James S. B. Chew, Vice President and General Manager of Intel Government Technologies, argues speed is now the decisive variable for U.S. defense readiness. Drawing on his GOMACTech 2026 keynote, he describes how digital-first practices—hardware-accurate digital twins, verification methodologies, and commercial-grade emulation—paired with domestic manufacturing can accelerate prototyping, reduce risk, and harden supply chains.
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Mark Gardner, Vice President and General Manager of the Packaging and Test Business Group at Intel Foundry, explains why AI and HPC are driving multi-die packages beyond single-reticle limits. He outlines EMIB bridge-based approaches— including EMIB-T with TSVs for improved power delivery—enabling larger die complexes with higher interconnect density and stronger power and thermal management.
Read the Blog
Intel Foundry has reached a notable systems foundry milestone with the demonstration of the world’s thinnest gallium nitride (GaN) chiplet, measuring just 19 micrometers. This research achievement highlights Intel Foundry’s ability to integrate compound semiconductors, advanced silicon process technology, and advanced packaging to address the increasing power and performance demands of AI and high-performance computing systems. By tightly integrating GaN power devices with silicon‑based digital control, this approach enables higher power density, improved efficiency, and more compact system designs, giving customers greater flexibility as they build heterogeneous, next-generation platforms. The breakthrough underscores Intel Foundry’s systems foundry strategy—bringing together process, packaging, and ecosystem innovation to support scalable performance and power efficiency for the AI era.
Read the Blog
EMIB-T Benefits Explained in New Video
The introduction of TSVs to our Embedded Multi-die Interconnect Bridge (EMIB) technology is driving increased performance for large package architectures. EMIB-M and EMIB-T are explained in a short video highlighting these industry-leading technologies. See how EMIB-T delivers superior power efficiency and bandwidth for demanding applications.
Watch the Video
Why Chip Packaging May Decide the Next Phase of the AI Boom
As AI models grow larger and more power‑hungry, performance gains hinge less on transistor scaling and more on how chips are assembled. In Wired, industry leaders explain why advanced packaging—linking compute, memory, and accelerators at scale—has become a critical bottleneck and strategic differentiator shaping the future of AI infrastructure.
Read the Blog
Prefer early access? Join the newsletter list and get news directly from Intel Foundry to your inbox.
Intel Foundry Showcases Defense-Ready Tech at GOMACTech
Fresh from GOMACTech 2026, Tao Zhou, Senior Principal Engineer at Intel, shares how Intel Foundry and partners are executing on secure, onshore microelectronics for defense. He highlights interoperable chiplets, advanced packaging, and system-level enablement, plus technical contributions across architecture, design sign-off reliability, and Intel 18A device innovations aimed at AI-ready, mission-critical systems.
Read the Blog
Domestic Manufacturing Accelerates Delivery of Mission-Critical Technology
James S. B. Chew, Vice President and General Manager of Intel Government Technologies, argues speed is now the decisive variable for U.S. defense readiness. Drawing on his GOMACTech 2026 keynote, he describes how digital-first practices—hardware-accurate digital twins, verification methodologies, and commercial-grade emulation—paired with domestic manufacturing can accelerate prototyping, reduce risk, and harden supply chains.
Read the Blog
Advanced Packaging Innovations Scaling Past Reticle Limits
Mark Gardner, Vice President and General Manager of the Packaging and Test Business Group at Intel Foundry, explains why AI and HPC are driving multi-die packages beyond single-reticle limits. He outlines EMIB bridge-based approaches— including EMIB-T with TSVs for improved power delivery—enabling larger die complexes with higher interconnect density and stronger power and thermal management.
Read the Blog