Regarding the continuous "battle" between innovation and trusted manufacturing, I find it very interesting how this battle is currently ongoing between high-NA and multi-patterning-low-NA EUV adoption/insertion in the coming nodes. I get the impression that
TSMC always tries to put trusted manufacturing first as they are simply so customer-oriented, especially now during 2025-2030, where this whole AI transition depends on TSMC's trusted execution for NVIDIA, AMD, Google, Apple and some other customers. TSMC must feel an enormous responsibility and opportunity to execute well supporting this AI transition.
Perhaps Intel was always a bit too-much R&D process innovation oriented where the R&D engineers had more cloud (Copy Exact!) versus the Fab engineers.
And this battle is ongoing regarding innovation and trusted manufacturing: there seems to be a strong lobby going on by Intel, IBM and ASML for (innovative tool) high-NA insertion at the 14A / A14 nodes, where TSMC seems to insist at staying at (multi-patterning) low-NA for 14A:
https://www.tomshardware.com/tech-i...igh-na-euv-for-1-4nm-class-process-technology
When asked whether A14 heavily relies on multi-patterning, Zhang responded that he could not comment on specifics, but said that TSMC's technology team had found a way to produce chips on a 1.4nm node without using High-NA EUV tools that provide an 8nm resolution compared to a 13.5nm resolution of Low-NA EUV systems.
"This is a great innovation from our technology team," said Zhang. "As long as they continue to find a way, obviously, we do not have to use High-NA EUV. Eventually, we will use it at some point. It is just so we need to find a right interception point, provide the maximum benefit, maximum return on investment."
It is noteworthy that TSMC's A14 will be succeeded by A14 with SPR backside power delivery in 2029, and it does not appear that the foundry will require High-NA EUV tools for this iteration either. To that end, it looks like, unlike Intel, which is set to start using next-generation EUV lithography machines with its 14A manufacturing technology to reduce the number of EUV exposures (read: multipatterning) and process steps in 2027 – 2028, TSMC has no plans to use High-NA EUV for mass production until at least 2030, or perhaps even later.
Stimulated by this wonderful analysis of SPIE-2025 (
https://semianalysis.com/2025/04/14/spie2025/) and the mentioning of the IBM-contribution by Luciana Meli, I just listened to her talk:
https://www.spiedigitallibrary.org/...erconnect-scaling-and/10.1117/12.3056559.full
ASML appears to be in the middle of this Intel-TSMC battle. ASML invested tremendously in high-NA EUV but their most important EUV-customer presently, TSMC, seems not (publicly) planning HVM with high-NA till perhaps 2030. And Intel needs/wants more support in the high-NA eco-system for innovation on resists and lobbying ASML for larger mask-sizes (to increase productivity):
https://bits-chips.com/article/asml-throws-weight-behind-bigger-euv-masks/
I have the impression that for now the monopolist foundry, TSMC, is winning this
innovation-vs-trusted manufacturing battle, as Intel has also indicated that its 14A process will have (multi-patterning) low-NA as an option for its foundry process:
https://www.tomshardware.com/pc-com...echnique-has-identical-yield-and-design-rules
Additionally, Intel’s claim that both production flows offer the same yields signals that there won’t be severe time-to-market repercussions if High-NA EUV development hits a snag, or if Intel chooses not to deploy it due to economics. Employing multi-patterning often reduces yields, but Intel's claim of yield parity speaks to the advances of modern multipatterning, particularly in the field of overlay technology.
Innovation versus trusted-manufacturing, the battle continuous.....
. 