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TSMC’s Advanced Packaging Capacity is fully booked for next two years by Nvidia and AMD

Daniel Nenni

Daniel Nenni

Admin
Staff member
TSMC, the world’s leading semiconductor manufacturer, has announced that its advanced packaging capacity is fully booked for the next two years. This development comes as Nvidia, AMD, and Guanghuida secure TSMC’s cutting-edge packaging technologies for their high-performance computing (HPC) ventures.

The focus on high-performance computing stems from the crucial role it plays in powering artificial intelligence (AI) tasks. TSMC anticipates a significant surge in revenue from AI processors, with projections indicating a doubling this year alone. Over the next five years, the compound annual growth rate for AI chips is expected to hit 50%, with AI processors projected to contribute over 20% of TSMC’s revenue by 2028.

image-12-1024x659.png

source: tsmc.com

Both Nvidia and AMD have secured TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) and System-on-Integrated-Chip (SoIC) advanced packaging capacities for their products. Nvidia’s flagship H100 chip, built on TSMC’s 4nm process, utilizes CoWoS packaging. Meanwhile, AMD’s MI300 series, manufactured using TSMC’s 5nm and 6nm processes, leverages SoIC for CPU and GPU integration before employing CoWoS with High Bandwidth Memory (HBM).

Guanghuida, a rising player in the AI chip market, has also booked TSMC’s packaging capacity. Their H100 chips, powered by TSMC’s 4nm process and CoWoS packaging, boast SK Hynix’s HBM for enhanced performance. Moreover, Guanghuida’s latest Blackwell architecture AI chip, based on TSMC’s advanced 4nm process, features upgraded HBM3e memory, doubling computing power compared to its predecessors.

The soaring demand for AI chips is fueled by global cloud service giants such as Amazon AWS, Microsoft, Google, and Meta, all vying for superiority in the AI server domain. With shortages from major manufacturers like Nvidia, AMD, and Guanghuida, these cloud behemoths are turning to TSMC to fulfill their orders, contributing to the chipmaker’s optimistic revenue projections.

To meet this escalating demand, TSMC is ramping up its production capacity for advanced packaging. By the end of this year, CoWoS monthly production is set to triple, reaching 45,000 to 50,000 wafers, while SoIC capacity is expected to double, reaching 5,000 to 6,000 wafers. By 2025, SoIC monthly production is projected to double again, hitting 10,000 wafers.

TSMC’s fully booked advanced packaging capacity signifies the accelerating pace of innovation in AI-driven computing, with key players strategically positioning themselves to capitalize on this potential market.

 
I have asked TSMC on several occasions if they will package non TSMC logic die with TSMC die and they have said no. Same thing for chiplets. It is a hard stance since Intel will accept other foundry die and are packaging Intel and TSMC die already but I understand since they are currently packing limited. I expect if a big TSMC customer mandated it TSMC would do it, but other than that do you see a business reason for TSMC package other foundry's die?
 
Daniel Nenni said:
I have asked TSMC on several occasions if they will package non TSMC logic die with TSMC die and they have said no. Same thing for chiplets. It is a hard stance since Intel will accept other foundry die and are packaging Intel and TSMC die already but I understand since they are currently packing limited. I expect if a big TSMC customer mandated it TSMC would do it, but other than that do you see a business reason for TSMC package other foundry's die?
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No, for now. Isn't that TSMC's advantage? Until someone beat TSMC.
 
Daniel Nenni said:
other than that do you see a business reason for TSMC package other foundry's die?
Click to expand...
I have two minds on this. Assuming you cut out all of the logic and memory IDMs, my understanding TSMC is the largest 2.5/3D packaging house (because my understanding is that OSAT 2.5/3D ecosystem is more rudimentary). On the one hand you may want to keep things locked down as that makes TSMC’s wafers sticker since the burden of switching others might offset the benefits of moving some dies to not TSMC. On the other hand that might be a mistake longer term. With Samsung and intel taking their packaging expertise to their foundry business, OSATs finally investing in advanced packaging, the relative ease of qualifying/designing a new package, the lower barrier of entry, and customers dragging TSMC towards UCIE I don’t think TSMC’s COWS moat is particularly large (unlike with wafers where it is immense). If we assume that advanced packaging becomes somewhat commoditized, and that TSMC eventually has even a single viable competitor on the leading edge then not allowing other foundry wafers could end up putting TSMC on an island. To put it another way as folks adopt other advanced packaging technologies the barrier of switching foundries becomes smaller. In this scenario the best way to solidify their wafer moat is to allow for other folks wafers. That way folks who do want to adopt a die or two of not TSMC can stay closet to TSMC’s ecosystem and use technology that will make their wafers perform at their best.

I don’t know which way is “better” or if either will work fine with the correct execution as we have examples of both working. Many IOS users are too ingrained to even consider alternatives such as android allowing Apple to maintain strong MSS and margins in spite of the fact that they haven’t been innovative for a long time. As an example of a failure of this locked down strategy one can just look to Windows servers getting eaten alive by Linux in the 90s/00s.

An example of the later working would be intel. Having one common arch that could run all software made the x86 ecosystem very popular and hard to uproot. To further solidify their moat intel would go onto define/co-optimize hardware standards and popular software (GCC, wintel, PCIE, USB, thunderbolt, etc) to make their CPUs more competitive than what silicon alone could achieve. As for an example of when opening up hurt more than it helped maybe IBM choosing x86 and MS for the PC or when they were forced to unbundle software from their computers back in the 60s?
 
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Daniel Nenni said:
I have asked TSMC on several occasions if they will package non TSMC logic die with TSMC die and they have said no. Same thing for chiplets. It is a hard stance since Intel will accept other foundry die and are packaging Intel and TSMC die already but I understand since they are currently packing limited. I expect if a big TSMC customer mandated it TSMC would do it, but other than that do you see a business reason for TSMC package other foundry's die?
Click to expand...
The answers from tsmc guys make sense. There are several strategic questions to be answered when tsmc build advanced package fabs or even provide so-call turn-key service.
1. What is the business reason tsmc had built mature package capacity or created mini assembly and test line which did not have economic scale? Why providing turn-key service and outsourcing it to OSAT? For more profit? Seems not
2. Why tsmc develop advanced package technologies and build capacity now? Why they compete with mature OSAT infrastructure in Taiwan?
The reasons I thought are two parts:
a. From key customers' request.
We saw it from Apple for AP package requirements, Xilinix CoWoS and now for nVidia and more. The original OSAT supply chain seems "can-not" support it.
b. From Foundry business requirement.
If there are bottleneck in package, assembly and testing, then tsmc business will be choked by it. This will be big business risk to be alleviated. For example, ASML acquired
Cymer lasers and invested in Carl Zeiss SMT for EUV lens to solve the bottlenecks. Then EUV development had been expedited. tsmc build their advanced package fabs now
have similar reason. Will they acquire or invest in OSAT companies?
Upon this, will tsmc package other foundry's chips? It could depend on customer's request and business requirements. I would not say it is not possible.
 
Daniel Nenni said:
I have asked TSMC on several occasions if they will package non TSMC logic die with TSMC die and they have said no. Same thing for chiplets. It is a hard stance since Intel will accept other foundry die and are packaging Intel and TSMC die already but I understand since they are currently packing limited. I expect if a big TSMC customer mandated it TSMC would do it, but other than that do you see a business reason for TSMC package other foundry's die?
Click to expand...

If the report is true that TSMC's advanced packaging capacity is fully booked for the next two years already, it doesn't make sense for TSMC to invest more money to package products involved other foundries' chips. Not only this is other foundry's own responsibility and business opportunities, but also it has the potential to get TSMC into anti trust troubles.
 
hist78 said:
If the report is true that TSMC's advanced packaging capacity is fully booked for the next two years already, it doesn't make sense for TSMC to invest more money to package products involved other foundries' chips. Not only this is other foundry's own responsibility and business opportunities, but also it has the potential to get TSMC into anti trust troubles.
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If advanced package capacity is the bottleneck of supply chain for customers' N3/N2 wafers manufactured in tsmc, then they need to invest more to support their customers' need and enable more N3/N2 revenue.
 
Misleading headline. According to semianalysis & Jeffries -- TSMC (typo, fixed) 2024 CoWoS is mainly Nvidia (40%-45%), AMD (10%) and the rest split between Broadcom & Amazon. Amazon is building a number of new data centers -- using many of their internally developed chips. Note that Broadcom CEO described in the latest ER report $10B in AI semiconductor sales in 2024 -- most (all?) of which is CoWoS.

Nvidia also has another source for CoWoS.
 
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The good news is that ramping a packaging facility takes much less time and much less money than building a fab so this is a very temporary bottleneck. So many surprises in the semiconductor industry.
 
MKWVentures said:
@Daniel Nenni

Who might want to use TSMC CoWoS Advanced packaging with other foundry die (Side note: CoWoS assembles packages from other companies).
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Good question. I think this is a future consideration since TSMC is very clear that they do not do it as of today. Once CoWos capacity opens up TSMC may allow it rather than have idle factories.
 
Who the hell is Guanghuida ? From the description they are just packaging NVIDIA H100s and Blackwell chips, not their own.

Guanghuida, a rising player in the AI chip market, has also booked TSMC’s packaging capacity. Their H100 chips, powered by TSMC’s 4nm process and CoWoS packaging, boast SK Hynix’s HBM for enhanced performance. Moreover, Guanghuida’s latest Blackwell architecture AI chip, based on TSMC’s advanced 4nm process, features upgraded HBM3e memory, doubling computing power compared to its predecessors.
Click to expand...
 
MKWVentures said:
@Daniel Nenni

Who might want to use TSMC CoWoS Advanced packaging with other foundry die (Side note: CoWoS assembles packages from other companies).
Click to expand...

For over more than the last 10 years, the Heterogeneous Roadmap (vision) has been that companies can buy chiplets from multiple suppliers and mix&match in the final package. (roadmap still says this today)

I've always questioned how this will evolve. TSMC's position makes total sense. Other companies like Amkor, Intel will try to be more of general supplier -- accepting chiplets from multiple sources.

If one of the big companies really pushes TSMC at some point -- I could see them accepting other chiplets. They do this today with HBMs.
 
ChrisGar said:
For over more than the last 10 years, the Heterogeneous Roadmap (vision) has been that companies can buy chiplets from multiple suppliers and mix&match in the final package. (roadmap still says this today)

I've always questioned how this will evolve. TSMC's position makes total sense. Other companies like Amkor, Intel will try to be more of general supplier -- accepting chiplets from multiple sources.

If one of the big companies really pushes TSMC at some point -- I could see them accepting other chiplets. They do this today with HBMs.
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I think the difference is that lots of companies assemble heterogeneous chips. ASE, Amkor, etc can do those. I have worked on those for a few companies. The only thing TSMC is a leader in is high performance CoWoS..... even then you can get similar options at OSATS.... So maybe people are choosing TSMC since they make the logic chip anyway? They still add HBM and IO from other companies packaging.
 
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