why poly(transistor gate) orientation check is significant in leading edge tech

[chowdaiah04]

what is the reason behind poly (transistor gate) orientation check in advanced process nodes ?

Basically the check is like all the standard cells , memories , IP's need to have same poly orientation ( either horizantal or vertical ) .

why not to use both orientations ?

 

[khaki]

Leading edge are still using immersion lithography with 193nm wavelength. To make sure they can print lines with a pitch far less than otherwise possible with immersion litho, they use a combination of OPC, source-mask optimization (SMO), etc. If the structure mostly consists of parallel straight lines, a dipole illumination can be used to improve litho. But that puts restriction on the layout; only unidirectional lines and only in one direction (not both) are allowed at the tightest pitch. Your DRC should check for this. Large structures are typically allowed to have bidirectional features, because the imperfections in the litho (a few nanometer) will not be a big problem.