what is reason for not allowing Mixed VT cells in a chip for FDSOI technology ?

[chowdaiah04]

Hi
In 22nm fdsoi technology , there were some design rules like VT spacing between SVT and LVT , SVT and HVT std cells
so it is not possible to allow mixed VT in a chip .
I want to know what was the reason for this ? is there any limitation from Manufacturing point of view ?
Please share your views ...

Thanks in advance !!

 

[khaki]

chowdaiah04, I do not have access to pdk, so cannot be specific (even I did I could not in public). You can still use different Vt in the chip same as any other technology. Like any other technology there is a minimum spacing rule between these Vts. In bulk technologies, Vts are defined by Vt adjust implants. So you have masks with minimum size and minimum spacing rules. In FDSOI, Vt is set by a combination of the polarity of well under the BOX, possibly metal workfunction, and whether or not SiGe is used in the PFET channel. Any of these need masks and bring in design rules. One possibility to reduce the spacing, is to use a longer gate length instead of using a higher Vt transistor. So say instead of placing a SVT cell next to LVT, you can use LVT cell with longer gate length. Your PDK and standard cell library should contain recommendations for this.

 

[Paul McLellan]

I don't have access to PDKs either, but one issue is that under FD-SOI the channel is fully depleted so there is no channel implant to vary. You can use FBB to control the tradeoff between power and speed but any given area of the chip has only one substrate voltage, it has to be done on a large scale (like power down or DVFS).

 

[Daniel Nenni]

Answer from good friend and industry expert who does have access to PDKs:

Contrary to bulk planar technologies where from the natural Vt of the transistor, Vt
modulation is obtained through implants, in FD-SOI there are several ways to trim
the Vt of the device, the main being:

- controlling the implantation of the wells (below the box), possible with FD-SOI only
- applying some light implant on the channel, like what done with FF
- controlling the gate length (true for all technologies)

About using wells for controlling the device Vt, this is unique to FD-SOI and of
course free (no extra masks required). When designing transistors in a standard
configuration (a Pwell below a Ngate, a Nwell below a Pgate) you get a regular Vt
device; when changing the well configuration (a Nwell below a Ngate, a Pwell below a
Pgate) in what we call "flip-well" configuration, the Vt is lowered by roughly 80mV
and we obtain low Vt devices.

To note this works not only on logic devices, but also on I/O devices and
transistors in bitcells leading to multiple Vts being available for thick oxide
transistors, and allowing mixing Vts in bitcells (not possible through implants in
other technologies).

Now, RVT and LVT devices are totally mixable, provided the design respects the well
distances and proper well polarizations.

While not being a problem at chip level or in full custom designs, you understand it
may be cumbersome realizing a digital block by std-cells mixing regular well and
flip well cells because of the extra space required (some fillers would be required
to separate RVT and LVT cells).

In practice, also digital blocks implementation is not a problem: in our experience
of numerous customer projects, blocks implementing a functionality have different
targets and hardly require mixing more than 2-3 Vts in a single block. When looking
at high speed blocks, you usually mix Vts around fast devices, when implementing
slow/low leakage blocks you mix Vts around slow devices.

Now, in our std-cells multi-channel libraries the contact to poly gate pitch can
accommodate channel length adaptation from Lmin=24nm up to 40nm, offering 4 Vt
modulation options (24-28-34-40nm) for each well configuration. This allows an
extremely wide leakage control between L=24nm (leakage = 1x) and L=40nm (leakage
1/50x); to reach the same with conventional technologies users have to mix 3 Vts.
And our multi-channel libraries are also highly competitive on area, being
gate-first minimum distances tighter than in other bulk planar technologies.

You understand the potential here. When implementing a SoC users can for example:

- implement a high (or medium) speed core with flip-well LVT cells, mixing
24-28-34-40nm cells (cells all have same footprint, and implementation flow is
exactly the same as with bulk planar technologies)

- implement a low speed, low energy video decoder with regular-well RVT cells, again
of course mixing 24-28-34-40nm multi-channel libraries for leakage optimization.
And of course LVT and RVT blocks can be easily mixed in a SoC.

 

[IanD]

Daniel, I think what you've described are the PDK rules for 28FDSOI. Global's 22FDSOI process uses the transistors developed for ST's 14FDSOI process, so the rules for this will be different.

 

[khaki]

Yes, IanD is correct, those are 28FD rules.

 

[Daniel Nenni]

Yes, IanD is correct, those are 28FD rules.

Yes, that is from the 28nm FD-SOI PDK. I will see if 22nm is different.

 

[Pawan Fangaria]

What I recollect from one of the most recent GF presentations on their FD-SOI process is that Vt can be changed dynamically. So, there may not be a need to mix between different Vt std cells.

 

[khaki]

Pawan, you still need a mix of different Vt cells. Dynamic Vt modulation was also an option in 28FD. The arrangement of using what ST calles RVT-line (i.e. LVT transistor with longer gate length as Dan described) was actually to allow neigboring transistors that might have different Vt to share the same well and body bias.

As IanD stated, in 14FD (and 22FDX that uses the same transistors) there are other possibilities. One is:

https://www.google.com/patents/US20140312423

I don't know if GF is using this in manufacturing, but one of their Ion-Ioff charts suggests so.

The other possibility is to use counter-doping the top portion of the well just below the BOX. So, you have for example a p+ layer just under the BOX in an n-well.

https://www.google.com/patents/US20130065366

This woeks in DC operation, since the resulting p-n diode does not have any current flowing. To make it work at ac it needs a bit of trick:

https://www.google.com/patents/US8969966

 

[Daniel Nenni]

Here you go:

The 22FDX technology provides a wide-range of Vt options and it supports Vt mixing and Selective Timing Bias (gate-sizing). The base device Vt offering can span nearly 6 orders of magnitude of leakage range for SoC design. The 22FDX PDKs and design starter kits provide this support.


There are four Vts in the base technology offering for logic devices.

• SLVT/LVT - created with flip-well
• RVT/HVT - created with conventional-well

Every ~1V potential change on the back-gate is about a 70mV change in the device Vt. Therefore, the switch from flip- to conventional-well means that the RVT/HVT devices are about 70mV higher Vt than the corresponding SLVT/LVT devices.


Multiple options exist for Vt mixing:

• LVT and HVT devices are easily derived out of the SLVT and the RVT devices, respectively. These devices provide very good Ioff separation for Vt mixing.
• The Vt of each of these four device types can be further adjusted with gate-length sizing.

The preferred implementation in dense, standard-cell, logic where Vt mixing for timing-closure / hold-margining is required would be as follows:

• SLVT/LVT (+ Lg sizing) blocks that can be forward body-biased to reduce active power (or for a frequency boost).
• RVT/HVT (+Lg sizing) blocks that can be reverse body-biased to reduce standby leakage

For analog devices, where area is not as critical and the devices are isolated from each other, the designer has more flexibility to utilize all four device types in the circuit and to even apply both forward and reverse body-bias to single-devices.

 

[khaki]

Dan,

There must be a typo here. As you pointed out the difference between flipped well and conventional well is about 70mV (exact number depends on the BOX thickness they used). That's equivalent to about one order of magnitude change in leakage. So, SLVT and LVT can be the same device built on flipped well and conventional well, respectively. SLVT (and its longer Lg that will be similar to LVT at nominal Lg) can be forward biased. LVT on conventional well is roughly where SLVT at longer Lg ends up to be and can be reverse biased.

RVT needs to be about 2 orders of magnitude lower leakage than SLVT, so you cannnot start with SLVT and put it on conventional well to create RVT. RVT and HVT need to be two new creatures, on flipped well and conventional well, respectively so that in total they cover 4 orders of magnitude of leakage (+2 with FBB SLVT and RBB HVT) to cover 6 orders of magnitude.

 

[Daniel Nenni]

Khaki:

There is no typo. There are multiple ways to form Vt flavors in an FD-SOI technology:

- Flip-/Conventional Well
- Gate-length sizing
- Forward-/Reverse body-bias
- Other approaches (used for LVT and HVT)

The 22FDX offering utilizes all these approaches to provide a large Ioff range at the SoC level and a wide range of mixable Vts for use in dense standard cell logic without area loss. There are also ways to create devices with even lower leakage which are included in the 22FDX-ull platform extension and not discussed in this thread.

To clarify your question, the 22FDX technology provides the following matrix of Vts in the base offering. Each ~1V of back-gate change is about 70mV of Vt shift or about 1 order of magnitude in leakage. I think you can see from this table that we can span nearly 6 orders of magnitude leakage with this offering. Vts are fully mixable in dense, standard-cell logic w/o area loss inside a given back-gate type (flip-well or conventional-well).

y-axis represents approximate leakage (or Vt).