TSMC's 2nm chips are officially launched.
On December 29, 2022, TSMC announced the mass production of its 3nm wafer foundry process.
In December 2025, the "final exam" for the 2nm process officially entered the grading stage.
Previously, the three major giants, TSMC, Samsung, and Intel, almost simultaneously announced that they would conquer the 2nm advanced process in Q4 2025, heating up the race for the top - tier chip technology. As the last week of Q4 arrived, under the high - profile attention of all parties in the industry, the biggest mystery in the semiconductor field this year finally unveiled its key prelude.
From the perspective of performance improvement, the design goal of N2 is to achieve a 10% - 15% performance improvement at the same power consumption and reduce power consumption by 25% - 30% at the same performance. For mixed designs including logic, analog, and SRAM, the transistor density is 15% higher than that of N3E. For pure logic designs, the transistor density is 20% higher than that of N3E.
TSMC's N2 process is the company's first process node to adopt Gate - All - Around nanosheet transistors (GAA). In this type of transistor, the gate completely surrounds the channel composed of horizontally stacked nanosheets. This geometry improves electrostatic control, reduces leakage, and enables smaller transistor sizes without sacrificing performance or energy efficiency, ultimately increasing transistor density. In addition, the N2 process also adds ultra - high - performance metal - insulator - metal (SHPMIM) capacitors to the power delivery network. The capacitance density of these capacitors is more than twice that of the previous - generation SHDMIM design, and the sheet resistance (Rs) and via resistance (Rc) are reduced by 50%, thereby improving power stability, performance, and overall energy efficiency.
Fab 20 in Baoshan and Fab 22 in Kaohsiung, both in Taiwan, China, are TSMC's first fabs for 2nm production. All of the 2nm production capacity of these two fabs in 2026 has been booked, with Apple accounting for more than half of the initial capacity. Other 2nm customers also include major chip manufacturers such as Qualcomm, MediaTek, AMD, and NVIDIA.
It is worth noting that TSMC is not the first company to announce the mass production of the 2nm process. Consistent with the development rhythm of the 3nm process before, Samsung once again took the lead in realizing the technological implementation.
On December 19, 2025, Samsung Electronics officially launched the world's first mobile application processor (AP) Exynos 2600 fabricated using the 2nm process and announced that this new chip had entered mass production. According to the introduction, this chip adopts a ten - core design based on Arm's latest architecture, with the CPU computing performance improved by up to 39% compared with the previous - generation product (Exynos 2500). At the same time, with the high - performance NPU, the generative AI performance is improved by 113%.
What is even more noteworthy is that Samsung introduced the Hot Path Blocking (HPB) technology for the first time in this chip, reducing the thermal resistance by up to 16%, attempting to completely end the negative label of performance degradation due to overheating of the Exynos 2100 and 2200 series chips. You know, it was the previous overheating problem that cost Samsung dearly. In the second half of 2022, Qualcomm, a core foundry customer, transferred all orders for processes below 4nm to TSMC. Even Samsung's own Mobile (MX) business unit abandoned its self - developed Exynos AP in the Galaxy S25 and instead used Qualcomm's Snapdragon 8 Elite chip, putting Samsung's foundry business in a difficult situation both internally and externally.
In fact, Samsung has a precedent for its aggressive strategy in advanced processes. As early as 2022, Samsung took the lead in the world to launch the 3nm process and became the first company to adopt GAAFET transistor technology. However, the yield problem has become its fatal shortcoming. In the first quarter of 2024, it was exposed that the yield of the 3nm process was less than 20%, and it is still struggling to improve. For the 2nm process this time, Samsung is betting on the GAA architecture again. Although the currently disclosed yield has stabilized at 50% - 60%, the industry still holds a wait - and - see attitude towards its large - scale supply capacity.
However, Samsung is not without cards. It is reported that Samsung Electronics' Foundry Division has conducted in - depth negotiations with AMD. The two parties plan to jointly develop next - generation CPU products based on the second - generation 2nm (SF2P) technology, and the target product may be the EPYC Venice series of processors. In terms of technical cooperation, Samsung will use Multi - Project Wafer (MPW) technology to provide chip prototype trial - production services for AMD. This technology, which allows multiple design projects to be integrated on the same wafer, can significantly reduce the initial development cost. According to people familiar with the matter, the two parties are expected to reach a final cooperation agreement early next year, which will be an important turning point for Samsung's foundry business.
In addition to TSMC and Samsung, two other companies are also participating in the 2nm process competition, namely Intel and Rapidus.
Intel recently also disclosed the relevant progress of its 18A process. The first client SoC based on the Intel 18A process, the next - generation AI PC processor codenamed Panther Lake, is being produced at Intel's latest fab. Panther Lake not only combines the high energy efficiency of Lunar Lake and the high performance of Arrow Lake, but also its multi - core performance is improved by 50% at the same power consumption, the graphics performance is improved by more than 40%, and the overall AI computing power is as high as 180 TOPS.
Gaosong, Vice President of Intel and General Manager of the Software Engineering and Client Products Division in China, said that Intel will officially launch Panther Lake at the CES in January next year.
Japanese wafer manufacturer Rapidus has started the test production of 2nm wafers and plans to promote the mass production of the 2nm process in its IIM - 1 fab in 2027. It is reported that the IIM - 1 fab has started the prototype production of test wafers using 2nm GAA transistor technology. Rapidus confirmed that the early test wafers have achieved the expected electrical characteristics, indicating that the fab equipment is operating normally and the process technology development is progressing smoothly.
Specifically for each manufacturer, TSMC still has the highest revenue and market share. Its revenue in the third quarter was $33.063 billion, higher than the $30.239 billion in the previous quarter, a quarter - on - quarter increase of 9.3%. Its market share also increased from 70.2% in the previous quarter to 71%, showing a further improvement.
The remaining nine companies: Samsung, SMIC, UMC, GlobalFoundries, Huahong, World Advanced, Jinghe Integrated, Tower Semiconductor, and Powerchip together account for 29% of the market share.
TSMC's Q3 financial report shows that advanced processes (defined as technologies of 7nm and below) accounted for a total of 74% of the total wafer revenue. Among them, the shipments of the 3nm process accounted for 23% of the total wafer revenue; the shipments of the 5nm process accounted for 37%; and the shipments of the 7nm process accounted for 14%. In Q3, TSMC's gross profit margin was 59.5%, an increase of 1.7 percentage points compared with 57.8% in the same period last year and an increase of 0.9 percentage points compared with 58.6% in the previous quarter.
The 2nm process is not only a technological competition but also a game of cost and pricing power.
The latest report shows that TSMC plans to expand its 2nm production capacity to 100,000 wafers per month in 2026. Compared with 3nm, the 2nm process has a better cost structure and stronger end - user demand, which are the core driving forces. In terms of price, market sources say that the price of TSMC's 2nm wafers will exceed $30,000, almost twice that of 4nm wafers.
According to the latest research by Semi Analysis, TSMC's average selling price (ASP) of wafers has shown a significant "cliff - like growth" in the past two decades. The 20 - year period from 2005 to now can be divided into two stages: 2005 - 2019 and 2019 - 2025.
Although the period from 2005 to 2019 was as long as 14 years, TSMC's average ASP of wafers only increased by $32 per wafer, with a compound annual growth rate (CAGR) of only 0.1%. The cost of goods sold (COGS) also had the same 0.1% growth rate. After 2019, the relevant data have all witnessed rapid growth. The average ASP increased by 133%, with a CAGR of up to 15.2%, while the cost growth was only 10.1%. Cumulatively, the profit per wafer increased by 3.3 times.
The reason is that TSMC started mass - producing the EUV process in 2018 and then increased production in 2019. Now, TSMC's average ASP of wafers has reached $7,000. In contrast, SMIC's average ASP of wafers in Q3 was only $924.
In November, market sources said that TSMC had notified its customers that since September, it has launched a four - year continuous price - increase plan for advanced processes below 5nm. The price increase will vary according to the procurement level and cooperation situation of individual customers. Among them, the quotation for the most popular 3nm process is expected to increase by at least a single - digit percentage. The industry describes this as "the first long - term price - increase action since the AI era."
Analysis believes that TSMC's rare four - year continuous price - increase plan echoes MediaTek's statement in its earnings conference that "it will adjust the chip selling price to reflect costs," which is expected to trigger the next wave of chip price increases. Market research institutions point out that with the prevalence of global inflation and the increase in TSMC's overseas factory construction and production costs, in order to maintain a high gross profit margin, it is estimated that the prices of TSMC's processes below 5nm will increase by about 5% - 10% starting from 2026.
It is reported that Samsung's 2nm process is expected to reach a monthly production capacity of 21,000 wafers by the end of 2026. In contrast, the company's target production in 2024 was 8,000 wafers per month, which means that Samsung may achieve a 163% growth in just two years.
As the 2nm process enters the "grading stage," a more thought - provoking question emerges: The limit of process miniaturization is approaching. Where will this decades - long competition go in the future? From the perspective of industry trends, 2nm is by no means the "end," but the core logic of the competition has shifted from "size miniaturization" to "multi - dimensional innovation."
TSMC said that the next - generation process A14 will adopt the second - generation GAAFET technology and the NanoFlex Pro standard cell architecture. It is expected to start risk production at the end of 2017, and large - scale mass production will not be achieved until 2028.
Samsung has also started the research and development of the "dream process" 1nm chips and plans to achieve mass production after 2029. Intel has also started researching the more advanced Intel 14A. Rapidus and the University of Tokyo will cooperate with the French semiconductor research institution Leti to jointly develop the basic technology for a new - generation semiconductor design with a circuit line width of 1nm.
The first breakthrough in multi - dimensional innovation lies in the diversified exploration of materials. As the potential of traditional silicon - based chips is gradually exhausted, the industry has begun to focus on new materials and new architectures. In the field of materials, third - generation semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN) have become the preferred choices for high - voltage and high - frequency scenarios due to their higher breakdown voltage and faster switching speed, and are rapidly penetrating into fields such as new - energy vehicles and 5G base stations. The more disruptive two - dimensional materials (such as graphene and molybdenum disulfide) are expected to break through the physical limitations of silicon - based materials and achieve more extreme size miniaturization and performance improvement. Although they still face many challenges in mass - production processes, they have become the key layout directions for global scientific research institutions and enterprises.
The second breakthrough in multi - dimensional innovation lies in the innovation of architectures. Chiplet technology breaks the traditional single - chip integration model. By packaging chip dies with different functions and different processes together, it realizes a customized "integration on demand" solution. It can use advanced processes to build core computing units and mature processes to achieve peripheral functions, reducing the overall cost. At the same time, it can improve system performance through multi - chip collaboration, becoming a key path to balance performance, cost, and power consumption. Industry giants such as Intel, AMD, and TSMC have launched relevant products and technical solutions.
The third breakthrough in multi - dimensional innovation lies in the continuous breakthrough of packaging technologies. Advanced packaging is not only a bridge connecting chips and circuit boards but also a core link to improve chip performance, integration, and reliability. In addition to the Chiplet packaging mentioned above, 3D IC packaging significantly shortens the interconnection distance and improves data transmission speed and integration density by vertically stacking chip dies. CoWoS (wafer - level system integration) packaging is designed for high - performance computing chips, realizing the integrated integration of chips, high - speed interconnections, and high - bandwidth memory, and has become the standard packaging solution for high - end GPUs and AI chips. The breakthrough in packaging technology enables chips with different processes and different materials to work together efficiently, providing a
该文观点仅代表作者本人，36氪平台仅提供信息存储空间服务。
On December 29, 2022, TSMC announced the mass production of its 3nm wafer foundry process.
In December 2025, the "final exam" for the 2nm process officially entered the grading stage.
Previously, the three major giants, TSMC, Samsung, and Intel, almost simultaneously announced that they would conquer the 2nm advanced process in Q4 2025, heating up the race for the top - tier chip technology. As the last week of Q4 arrived, under the high - profile attention of all parties in the industry, the biggest mystery in the semiconductor field this year finally unveiled its key prelude.
01
TSMC Submits Its Answers for 2nm
On Monday this week, Semiconductor Industry Insights noticed that TSMC issued a statement on its official 2nm technology webpage, stating: "TSMC's 2nm (N2) technology has started mass production in the fourth quarter of 2025 as planned."
From the perspective of performance improvement, the design goal of N2 is to achieve a 10% - 15% performance improvement at the same power consumption and reduce power consumption by 25% - 30% at the same performance. For mixed designs including logic, analog, and SRAM, the transistor density is 15% higher than that of N3E. For pure logic designs, the transistor density is 20% higher than that of N3E.
TSMC's N2 process is the company's first process node to adopt Gate - All - Around nanosheet transistors (GAA). In this type of transistor, the gate completely surrounds the channel composed of horizontally stacked nanosheets. This geometry improves electrostatic control, reduces leakage, and enables smaller transistor sizes without sacrificing performance or energy efficiency, ultimately increasing transistor density. In addition, the N2 process also adds ultra - high - performance metal - insulator - metal (SHPMIM) capacitors to the power delivery network. The capacitance density of these capacitors is more than twice that of the previous - generation SHDMIM design, and the sheet resistance (Rs) and via resistance (Rc) are reduced by 50%, thereby improving power stability, performance, and overall energy efficiency.
Fab 20 in Baoshan and Fab 22 in Kaohsiung, both in Taiwan, China, are TSMC's first fabs for 2nm production. All of the 2nm production capacity of these two fabs in 2026 has been booked, with Apple accounting for more than half of the initial capacity. Other 2nm customers also include major chip manufacturers such as Qualcomm, MediaTek, AMD, and NVIDIA.
It is worth noting that TSMC is not the first company to announce the mass production of the 2nm process. Consistent with the development rhythm of the 3nm process before, Samsung once again took the lead in realizing the technological implementation.
02
2nm: Samsung's All - or - Nothing Battle in Foundry
For Samsung, this battle for the first - to - market of the 2nm process is an all - or - nothing battle for its foundry business.On December 19, 2025, Samsung Electronics officially launched the world's first mobile application processor (AP) Exynos 2600 fabricated using the 2nm process and announced that this new chip had entered mass production. According to the introduction, this chip adopts a ten - core design based on Arm's latest architecture, with the CPU computing performance improved by up to 39% compared with the previous - generation product (Exynos 2500). At the same time, with the high - performance NPU, the generative AI performance is improved by 113%.
What is even more noteworthy is that Samsung introduced the Hot Path Blocking (HPB) technology for the first time in this chip, reducing the thermal resistance by up to 16%, attempting to completely end the negative label of performance degradation due to overheating of the Exynos 2100 and 2200 series chips. You know, it was the previous overheating problem that cost Samsung dearly. In the second half of 2022, Qualcomm, a core foundry customer, transferred all orders for processes below 4nm to TSMC. Even Samsung's own Mobile (MX) business unit abandoned its self - developed Exynos AP in the Galaxy S25 and instead used Qualcomm's Snapdragon 8 Elite chip, putting Samsung's foundry business in a difficult situation both internally and externally.
In fact, Samsung has a precedent for its aggressive strategy in advanced processes. As early as 2022, Samsung took the lead in the world to launch the 3nm process and became the first company to adopt GAAFET transistor technology. However, the yield problem has become its fatal shortcoming. In the first quarter of 2024, it was exposed that the yield of the 3nm process was less than 20%, and it is still struggling to improve. For the 2nm process this time, Samsung is betting on the GAA architecture again. Although the currently disclosed yield has stabilized at 50% - 60%, the industry still holds a wait - and - see attitude towards its large - scale supply capacity.
However, Samsung is not without cards. It is reported that Samsung Electronics' Foundry Division has conducted in - depth negotiations with AMD. The two parties plan to jointly develop next - generation CPU products based on the second - generation 2nm (SF2P) technology, and the target product may be the EPYC Venice series of processors. In terms of technical cooperation, Samsung will use Multi - Project Wafer (MPW) technology to provide chip prototype trial - production services for AMD. This technology, which allows multiple design projects to be integrated on the same wafer, can significantly reduce the initial development cost. According to people familiar with the matter, the two parties are expected to reach a final cooperation agreement early next year, which will be an important turning point for Samsung's foundry business.
In addition to TSMC and Samsung, two other companies are also participating in the 2nm process competition, namely Intel and Rapidus.
Intel recently also disclosed the relevant progress of its 18A process. The first client SoC based on the Intel 18A process, the next - generation AI PC processor codenamed Panther Lake, is being produced at Intel's latest fab. Panther Lake not only combines the high energy efficiency of Lunar Lake and the high performance of Arrow Lake, but also its multi - core performance is improved by 50% at the same power consumption, the graphics performance is improved by more than 40%, and the overall AI computing power is as high as 180 TOPS.
Gaosong, Vice President of Intel and General Manager of the Software Engineering and Client Products Division in China, said that Intel will officially launch Panther Lake at the CES in January next year.
Japanese wafer manufacturer Rapidus has started the test production of 2nm wafers and plans to promote the mass production of the 2nm process in its IIM - 1 fab in 2027. It is reported that the IIM - 1 fab has started the prototype production of test wafers using 2nm GAA transistor technology. Rapidus confirmed that the early test wafers have achieved the expected electrical characteristics, indicating that the fab equipment is operating normally and the process technology development is progressing smoothly.
03
The Price Storm Sweeps In
In Q3 2025, the revenue of the world's top ten wafer foundries reached $45.086 billion, higher than the $41.718 billion in the previous quarter, a quarter - on - quarter increase of 8.1%.Specifically for each manufacturer, TSMC still has the highest revenue and market share. Its revenue in the third quarter was $33.063 billion, higher than the $30.239 billion in the previous quarter, a quarter - on - quarter increase of 9.3%. Its market share also increased from 70.2% in the previous quarter to 71%, showing a further improvement.
The remaining nine companies: Samsung, SMIC, UMC, GlobalFoundries, Huahong, World Advanced, Jinghe Integrated, Tower Semiconductor, and Powerchip together account for 29% of the market share.
TSMC's Q3 financial report shows that advanced processes (defined as technologies of 7nm and below) accounted for a total of 74% of the total wafer revenue. Among them, the shipments of the 3nm process accounted for 23% of the total wafer revenue; the shipments of the 5nm process accounted for 37%; and the shipments of the 7nm process accounted for 14%. In Q3, TSMC's gross profit margin was 59.5%, an increase of 1.7 percentage points compared with 57.8% in the same period last year and an increase of 0.9 percentage points compared with 58.6% in the previous quarter.
The 2nm process is not only a technological competition but also a game of cost and pricing power.
The latest report shows that TSMC plans to expand its 2nm production capacity to 100,000 wafers per month in 2026. Compared with 3nm, the 2nm process has a better cost structure and stronger end - user demand, which are the core driving forces. In terms of price, market sources say that the price of TSMC's 2nm wafers will exceed $30,000, almost twice that of 4nm wafers.
According to the latest research by Semi Analysis, TSMC's average selling price (ASP) of wafers has shown a significant "cliff - like growth" in the past two decades. The 20 - year period from 2005 to now can be divided into two stages: 2005 - 2019 and 2019 - 2025.
Although the period from 2005 to 2019 was as long as 14 years, TSMC's average ASP of wafers only increased by $32 per wafer, with a compound annual growth rate (CAGR) of only 0.1%. The cost of goods sold (COGS) also had the same 0.1% growth rate. After 2019, the relevant data have all witnessed rapid growth. The average ASP increased by 133%, with a CAGR of up to 15.2%, while the cost growth was only 10.1%. Cumulatively, the profit per wafer increased by 3.3 times.
The reason is that TSMC started mass - producing the EUV process in 2018 and then increased production in 2019. Now, TSMC's average ASP of wafers has reached $7,000. In contrast, SMIC's average ASP of wafers in Q3 was only $924.
In November, market sources said that TSMC had notified its customers that since September, it has launched a four - year continuous price - increase plan for advanced processes below 5nm. The price increase will vary according to the procurement level and cooperation situation of individual customers. Among them, the quotation for the most popular 3nm process is expected to increase by at least a single - digit percentage. The industry describes this as "the first long - term price - increase action since the AI era."
Analysis believes that TSMC's rare four - year continuous price - increase plan echoes MediaTek's statement in its earnings conference that "it will adjust the chip selling price to reflect costs," which is expected to trigger the next wave of chip price increases. Market research institutions point out that with the prevalence of global inflation and the increase in TSMC's overseas factory construction and production costs, in order to maintain a high gross profit margin, it is estimated that the prices of TSMC's processes below 5nm will increase by about 5% - 10% starting from 2026.
It is reported that Samsung's 2nm process is expected to reach a monthly production capacity of 21,000 wafers by the end of 2026. In contrast, the company's target production in 2024 was 8,000 wafers per month, which means that Samsung may achieve a 163% growth in just two years.
As the 2nm process enters the "grading stage," a more thought - provoking question emerges: The limit of process miniaturization is approaching. Where will this decades - long competition go in the future? From the perspective of industry trends, 2nm is by no means the "end," but the core logic of the competition has shifted from "size miniaturization" to "multi - dimensional innovation."
TSMC said that the next - generation process A14 will adopt the second - generation GAAFET technology and the NanoFlex Pro standard cell architecture. It is expected to start risk production at the end of 2017, and large - scale mass production will not be achieved until 2028.
Samsung has also started the research and development of the "dream process" 1nm chips and plans to achieve mass production after 2029. Intel has also started researching the more advanced Intel 14A. Rapidus and the University of Tokyo will cooperate with the French semiconductor research institution Leti to jointly develop the basic technology for a new - generation semiconductor design with a circuit line width of 1nm.
The first breakthrough in multi - dimensional innovation lies in the diversified exploration of materials. As the potential of traditional silicon - based chips is gradually exhausted, the industry has begun to focus on new materials and new architectures. In the field of materials, third - generation semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN) have become the preferred choices for high - voltage and high - frequency scenarios due to their higher breakdown voltage and faster switching speed, and are rapidly penetrating into fields such as new - energy vehicles and 5G base stations. The more disruptive two - dimensional materials (such as graphene and molybdenum disulfide) are expected to break through the physical limitations of silicon - based materials and achieve more extreme size miniaturization and performance improvement. Although they still face many challenges in mass - production processes, they have become the key layout directions for global scientific research institutions and enterprises.
The second breakthrough in multi - dimensional innovation lies in the innovation of architectures. Chiplet technology breaks the traditional single - chip integration model. By packaging chip dies with different functions and different processes together, it realizes a customized "integration on demand" solution. It can use advanced processes to build core computing units and mature processes to achieve peripheral functions, reducing the overall cost. At the same time, it can improve system performance through multi - chip collaboration, becoming a key path to balance performance, cost, and power consumption. Industry giants such as Intel, AMD, and TSMC have launched relevant products and technical solutions.
The third breakthrough in multi - dimensional innovation lies in the continuous breakthrough of packaging technologies. Advanced packaging is not only a bridge connecting chips and circuit boards but also a core link to improve chip performance, integration, and reliability. In addition to the Chiplet packaging mentioned above, 3D IC packaging significantly shortens the interconnection distance and improves data transmission speed and integration density by vertically stacking chip dies. CoWoS (wafer - level system integration) packaging is designed for high - performance computing chips, realizing the integrated integration of chips, high - speed interconnections, and high - bandwidth memory, and has become the standard packaging solution for high - end GPUs and AI chips. The breakthrough in packaging technology enables chips with different processes and different materials to work together efficiently, providing a
该文观点仅代表作者本人，36氪平台仅提供信息存储空间服务。
Did these people even use an editor?