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6-track cell height scaling trend shows an interesting comparison between TSMC and Intel. PowerVia gave opportunity to relax the track pitch at Intel 18A. In the meantime, the track pitch scaling slowed down dramatically for TSMC. Perhaps it's coincidental with nanosheet introduction?
I think I understand what you are trying to get at, but why present it in this way? None of these processes use 6 M0 tracks (other than N7 and N2), and metal track reduction has been a key method of delivering density improvements in the late 2010s/early 2020s. I feel like a better plot to show your idea would be cell height gen over gen overlaid with a plot for MMP gen over gen.
I don't really think "track pitch scaling slowing for TSMC" is a TSMC problem. MMP scaling has been slowing for a while now. And as you note, Intel inverse scaled MMP on 18A.
The number of metal tracks is limited due to routibility concerns. As far as I know, nanosheets don't hurt this. In fact, for a given drive area nanosheets can fit into a smaller cell height than an equivalent finFET CMOS pair (exception being if your nanosheet is the same width as a single fin finFET device). But back to routing, from what I have heard from design/ecosystem folks, 7 M0 tracks (4 signal lines plus 2 1.5x MMP power rails) is a cozy place for designers to be. If you want to go to less than 4 signal lines you can't really properly route everything. More reasonable is to narrow the power rails to somewhere between 1x and 1.5x MMP, and you can go down to 6 M0 tracks at the minimum. But RC will kill your final chip's performance if you do that, so not ideal. If you fully architect your standard cells around BSPDN then you can in theory go down to 4 M0 tracks, since all you need is those 4 signal lines (assuming you can get your devices small enough to fit in that kind of space). If you can go to BS-signaling, then I suppose you can go down to probably 3 M0 tracks.
The chart looks even wonkier with HP libs. Using the VLSI cover photo Intel's M0P on 18A HP is 36nm rather than 32nm (18A HP presumed same size as 20A based on i3 HP being same size as i4) than HD, and because 18A HP is significantly denser than N3E HP (upwards of 20%). Don't have N2 HP data, but I would guess somewhere near 18A HP in that 190-170 range based on TSMC's trend of new HP cell being similar in size to last gen HD cell and about 9 M0 tracks tall. A HP cell chart would also look funky because the intel 4/3 HP cell is 17% shorter than the N5 HP cell, despite M0p being 7% fatter on i4/3.
Each metal line is a "track", not just M2 lines. Scotten likes to look at up to M2 since you go up to that level to make more complex logic cells and because beyond M2 my understanding is designers are more so looking about block routing rather than individual cells. Simpler cells can be done without going to M2. Tanj has a blog where he discussed making his own standard cell library for a fictitious process node. For his made up process he used the same pitch gearings as i4/3 because apparently that 7/8 M0 tracks with a 1:1 ratio to fins, 1:1 M1 ratio to CPP, and 5 M2 tracks was super cozy. If memory serves he could do a NAND gate while only using minimal M1 routing resources.
I think M0 and M2 are both useful to look at depending on what we are trying to talk about. But when talking about the scale of individual devices how they are routed and the impacts of BSPDN, M0 is the most useful thing to look at. As an example M2 tracks count between 18A and I3 is unchanged. But if you look at M0 tracks are down 2. On account of losing those power rails. Now if you look at the M2 tracks Intel could have in theory gone smaller than 5 because surely at least 1/5 of the M2 tracks for a given cell must have been to supply the M0 power rails. They could have gone to like 40nm M2 and 4 tracks at their same cell height. But for whatever reason Intel decided to keep the 5 M2 tracks but have them all be for signal routing rather than split among signals and power.
