TSMC Is Reportedly Skipping High-NA EUV For The A14 (1.4nm) Process; Prioritizing Cost-Efficiency Over Performance

[fansink]

It seems like the Taiwan giant won't be jumping onto the High-NA EUV bandwagon anytime soon. It has been revealed that the firm will skip the lithography for the A14 process.

TSMC Now Gets Behind The Likes of Intel Foundry When It Comes To High-NA EUV Adoption, Will Rely On Older Technologies

When adopting newer elements in semiconductors, TSMC has been a pioneer for several years, and is often the trend-setter. But now, it seems like the firm will skip using the High-NA EUV lithography tool for its A14 process, as it will rely on the more conventional 0.33-NA EUV technology. This was revealed at the NA Technology Symposium, where TSMC's SVP Kevin Zhang announced the development (via Bits & Chips). With this, it is safe to say that Intel Foundry and several DRAM manufacturers now have a "technological" edge over TSMC.

TSMC will not be using high-NA EUV lithography to pattern A14 chips, manufacturing of which is scheduled to start in 2028. From 2 nanometers to A14, we don’t have to use high-NA, but we can continue to maintain similar complexity in terms of processing steps.

Each generation of technology, we try to minimize the number of mask increases. This is very important to provide a cost-efficient solution - TSMC's Kevin Zhang

Well, the primary reason why TSMC sees high-NA as something insignificant for the A14 process is that with the relevant lithography tools, the Taiwan giant could witness up to a 2.5x rise in costs compared to traditional EUV methods, and this will ultimately make the A14 node much more expensive to produce, which means that its adoption in consumer products would get difficult. The Taiwan giant is relying on chip designs and capabilities, but this certainly doesn't mean the company won't employ high-NA EUV for future processes, as it plans to utilize it for the A14P node.

One of the other reasons attributed to high-NA driving up costs is that TSMC's A14 would require multiple masks for a single layer of chip design, and using the latest lithography tools simply means the Taiwan giant is driving up costs without much benefit. Instead, by focusing on 0.33-NA EUV, TSMC can use multi-patterning techniques to maintain the same level of design complexity without needing the extreme precision of high-NA EUV, ultimately keeping production costs lower.

Interestingly, TSMC's decision to leave high-NA EUV behind does put the company behind the likes of Intel Foundry in adopting the latest tools, since Team Blue is said to utilize high-NA for the 18A process, which is expected to drop as soon as next year. With A14P targeted by 2029, TSMC would see at least a four-year delay in adopting high-NA compared to its counterparts, which could be a decision that can give competitors an edge.

TSMC Is Reportedly Skipping High-NA EUV For The A14 (1.4nm) Process; Prioritizing Cost-Efficiency Over Performance

TSMC won't jump onto the High-NA EUV bandwagon, as it has been revealed that the firm will skip the lithography for the A14 process.

wccftech.com

 

[Daniel Nenni]

This was actually disclosed at last year's TSMC Tech Symposium. It is both cost and capacity. TSMC will need dozens of those HNA-EUV systems and special built fabs for HNA-EUV HVM.

"With this, it is safe to say that Intel Foundry and several DRAM manufacturers now have a "technological" edge over TSMC."

This is comical. DRAM manufacturers now have an edge over TSMC? Do you think Muhammad Zuhair is trying to be funny or is he just clueless?

I'm sure Intel 14A and HNA-EUV will be discussed tomorrow at the Intel Foundry event so stay tuned. Exciting times in the semiconductor ecosystem, absolutely.

 

[fansink]

This was actually disclosed at last year's TSMC Tech Symposium. It is both cost and capacity. TSMC will need dozens of those HNA-EUV systems and special built fabs for HNA-EUV HVM.

"With this, it is safe to say that Intel Foundry and several DRAM manufacturers now have a "technological" edge over TSMC."

This is comical. DRAM manufacturers now have an edge over TSMC? Do you think Muhammad Zuhair is trying to be funny or is he just clueless?

I'm sure Intel 14A and HNA-EUV will be discussed tomorrow at the Intel Foundry event so stay tuned. Exciting times in the semiconductor ecosystem, absolutely.

It's getting progressively harder to trust ~news sources.

Thank goodness SemiWiki has people like you that are steeped in various arts to help filter the noise.

 

[Paul2]

This is comical. DRAM manufacturers now have an edge over TSMC?

How many decades ago did TSMC try to make DRAM?

 

[Jozo035]

This was actually disclosed at last year's TSMC Tech Symposium. It is both cost and capacity. TSMC will need dozens of those HNA-EUV systems and special built fabs for HNA-EUV HVM.

"With this, it is safe to say that Intel Foundry and several DRAM manufacturers now have a "technological" edge over TSMC."

This is comical. DRAM manufacturers now have an edge over TSMC? Do you think Muhammad Zuhair is trying to be funny or is he just clueless?

I'm sure Intel 14A and HNA-EUV will be discussed tomorrow at the Intel Foundry event so stay tuned. Exciting times in the semiconductor ecosystem, absolutely.

Could this give edge to In memory processing? Probably helping wider adoption (hurting traditional ASIC-s). Few HNA steps plus many SAQP.

I know that it's not exactly DRAM and also probably not something author of original article meant...

 

[Fred Chen]

The author of this article doesn't know what he is talking about it, as he writes that Intel 18A will use High-NA.

Interestingly, TSMC's decision to leave high-NA EUV behind does put the company behind the likes of Intel Foundry in adopting the latest tools, since Team Blue is said to utilize high-NA for the 18A process, which is expected to drop as soon as next year.

 

[SaberG]

PPAC rules . It means TSMC counts pros and cons . After detailed consideration, TSMC believes Intel or SUMSUNG's High-NA EUV technology can't challenge its superority.

 

[siliconbruh999]

I think TSMC is going to let Intel/Whoever do the hard work when there is a ecosystem they will just tap into it saving cost and minimizing risk.

 

[nghanayem]

PPAC rules . It means TSMC counts pros and cons . After detailed consideration, TSMC believes Intel or SUMSUNG's High-NA EUV technology can't challenge its superority.

You say that as if it isn't the right PPAC choice for Intel. Also Samsung hasn't made a public commitment to anything. Not every process is the same and what works well for one process won't necessarily work for another. As an example Intel by fully embracing BSPD can use much wider metals for the same cell size so Intel is more likely to be using direct print than TSMC on a given node. high-NA direct print vs EUV double good. Double highNA vs double lowNA not so much. TSMC would seemingly be in multipatterning with or without high-NA so the value proposition might be less. But maybe not since they supposedly said A14P will use high-NA so that just doesn't really seem like a condemnation of high NA, but TSMC being conservative on cutting it in like they were with EUV and like Intel not being married to one specific approach on 14A. An older example is SAC on Intel 22nm. TSMC 20nm and 16FF didn't have SAC. Intel liked the extra EPE margin and yield this gave. TSMC got a cost saving from this and figured out how to have good yield without the SAC. And then on N7 and N5 they didn't even attempt to do SAC, but then on N3 and 10FF they did have SAC. Often times what is best changes as the requirements and capabilities change.

 

[IanD]

For TSMC, having a "technological advantage" which doesn't improve PPA but does increase C (and can't scale up capacity fast enough) would be pointless and counterproductive willy-waving, not a good business decision...

OTOH Intel do have a bit of a track record recently for prioritising willy-waving over good business... ;-)

 

[nghanayem]

For TSMC, having a "technological advantage" which doesn't improve PPA but does increase C (and can't scale up capacity fast enough) would be pointless and counterproductive willy-waving, not a good business decision...

I mean yeah. But you say that as if there will never be any situations from now till the end of time where high-NA will ever be more cost effective than low NA. Intel has said time and time again they will ONLY pull the trigger if it is the best PPAC path and that based on the data they see, that this cost crossover occurs in the 14A timeframe. TSMC agrees since they will use it on A14P. Unless you believe A14P will be a PPAC regression over A14 your comment doesn't agree with the public statements of either of the experts.

OTOH Intel do have a bit of a track record recently for prioritising willy-waving over good business... ;-)

And what example do you have for that?

 

[Fred Chen]

You say that as if it isn't the right PPAC choice for Intel. Also Samsung hasn't made a public commitment to anything. Not every process is the same and what works well for one process won't necessarily work for another. As an example Intel by fully embracing BSPD can use much wider metals for the same cell size so Intel is more likely to be using direct print than TSMC on a given node. high-NA direct print vs EUV double good. Double highNA vs double lowNA not so much. TSMC would seemingly be in multipatterning with or without high-NA so the value proposition might be less. But maybe not since they supposedly said A14P will use high-NA so that just doesn't really seem like a condemnation of high NA, but TSMC being conservative on cutting it in like they were with EUV and like Intel not being married to one specific approach on 14A. An older example is SAC on Intel 22nm. TSMC 20nm and 16FF didn't have SAC. Intel liked the extra EPE margin and yield this gave. TSMC got a cost saving from this and figured out how to have good yield without the SAC. And then on N7 and N5 they didn't even attempt to do SAC, but then on N3 and 10FF they did have SAC. Often times what is best changes as the requirements and capabilities change.

So far High-NA still gives bad images even at 28 nm pitch. To be fair low-NA should be the same.

High-NA has less depth of focus so needs thinner resist, which tends to be more defective.

 

[nghanayem]

So far High-NA still gives bad images even at 28 nm pitch. To be fair low-NA should be the same.

View attachment 3116
High-NA has less depth of focus so needs thinner resist, which tends to be more defective.

That same statement could be said of regular EUV too. DUV uses far thicker resits and is far less defective than EUV per pass, but you hardly see logic folks using multipaterning DUV for much these days. Non spacer based quad patterning was dead before low-NA EUV even hit its stride. The one final application of pitch quartering (fin patterning) is dead. The most recent teardowns even show examples of the big 3 have even replacing DUV double patterned layers with direct print EUV just to get those 3-4 month cycle times and random non-litho defects under control. Intel also made the surprising (at least to me) claim that the high NA (on whatever layers they found high-NA useful for) and low NA versions of 14A were showing matched defectivity. Now, does that mean Intel is using 18 layers of high-NA and 0 layers of low-NA on 14A? Almost certainly NOT. But clearly it indicates that high-NA isn't some 1-2 decade out technology like some people sometimes make it out to be, and there are at least some applications where it is ready for the prime-time. I have long been of the opinion that high-NA was never going to be (nor was anyone seriously considering it to be) some universal lithography platform. But then again neither was EUV, or immersion-DUV, or dry-DUV... It is always about the best tool for the job when comparing cycle time, total wafer cost, TTM, and design ease of use. Logicly TSMC wouldn't also be moving in the direction of a gradual/seamless high-NA insertion at the earliest possible intercept point (14"A" class nodes because 2"nm" class nodes were too deep into development for a high-NA insertion to ever make sense) if high-NA was some unmitigated disaster and strictly inferior technology with no reasonable use case.

 

[fansink]

So far High-NA still gives bad images even at 28 nm pitch. To be fair low-NA should be the same.

View attachment 3116
High-NA has less depth of focus so needs thinner resist, which tends to be more defective.

Isn’t the focal DOF for Low-NA systems like 3 times higher than for High-NA systems.

 

[Fred Chen]

That same statement could be said of regular EUV too. DUV uses far thicker resits and is far less defective than EUV per pass, but you hardly see logic folks using multipaterning DUV for much these days. Non spacer based quad patterning was dead before low-NA EUV even hit its stride.

LELELELE was mainly shown by Samsung at 8nm if I recall correctly. The difficult with more than two LEs is the CD/pitch ratio is too low, so NILS (normalized image log-slope) is bad.

The one final application of pitch quartering (fin patterning) is dead.

This I doubt, since the fin pitch is so small. EUV DP still too expensive and more issues than DUV SAPQ.

The most recent teardowns even show examples of the big 3 have even replacing DUV double patterned layers with direct print EUV just to get those 3-4 month cycle times and random non-litho defects under control.

DUV LELE is a pretty high yield and low cost process but if you have an EUV machine, those layers are the best opportunity for direct print.

Intel also made the surprising (at least to me) claim that the high NA (on whatever layers they found high-NA useful for) and low NA versions of 14A were showing matched defectivity.

Yes, since there are pitches where High-NA and Low-NA overlap in imaging, such as 28 nm and 30 nm. I.e., the image construction is exactly the same at the wafer.

Now, does that mean Intel is using 18 layers of high-NA and 0 layers of low-NA on 14A? Almost certainly NOT. But clearly it indicates that high-NA isn't some 1-2 decade out technology like some people sometimes make it out to be, and there are at least some applications where it is ready for the prime-time. I have long been of the opinion that high-NA was never going to be (nor was anyone seriously considering it to be) some universal lithography platform. But then again neither was EUV, or immersion-DUV, or dry-DUV... It is always about the best tool for the job when comparing cycle time, total wafer cost, TTM, and design ease of use.

Yes, if you already bought EUV, you have to use it. But it's not a story of missing out on a higher NA or shorter wavelength is fatal. Multipatterning efficiency will improve, this will help DUV as well.

 

[Fred Chen]

Isn’t the focal DOF for Low-NA systems like 3 times higher than for High-NA systems.

Yes, inversely proportional to (NA)^2.

 

[nghanayem]

LELELELE was mainly shown by Samsung at 8nm if I recall correctly. The difficult with more than two LEs is the CD/pitch ratio is too low, so NILS (normalized image log-slope) is bad.

That is my memory as well. I mostly included it because I think it is funny. I don't think anything in industry has ever looked that obviously impractical. When Samsung was doing that, TSMC's DUV SALELE flow (which I think debuted on N7, but maybe it was on 10FF) would have been unknown to Samsung. So no shame for not trying what they didn't know existed. But I am frankly astounded they didn't use spacer based pitch division. They used it for NAND and DRAM, but they went for LE4 instead.

This I doubt, since the fin pitch is so small. EUV DP still too expensive and more issues than DUV SAPQ.

Pitch multiplication is not compatible with GAA nanosheet formation. Full stop. I have never once seen a single academic paper ever do nanosheet formation with anything other than direct print lithography. EDIT: I guess you could do it. But you lose the fine-grained variable device widths even within the same block. And GAA with fixed device width removes a lot of the incentive of going to GAA in the first place.

DUV LELE is a pretty high yield and low cost process

No disagreements there. Same with SAPD and DUV SALELE. All are battle test techniques at this point. But when we are talking 100+ mask layers like I would expect from A14 (and in all likelihood N2), those random defects rapidly eat into your "total DD budget".

but if you have an EUV machine, those layers are the best opportunity for direct print.

Yes, but also no. Nobody just buys extra litho tools for a rainy day. If you have an EUV machine, it is because your specifically bought it and needed that capacity based on the number of EUV layers and the wafer starts. My argument here is that if people are doing things that could be done with DUV double patterning, it is because the total wafer cost went down (even though litho exposure costs went up) or the cost is close enough that the cycle time and or design EOU offered a better TVO.

Yes, since there are pitches where High-NA and Low-NA overlap in imaging, such as 28 nm and 30 nm. I.e., the image construction is exactly the same at the wafer.

Good to know.

Yes, if you already bought EUV, you have to use it. But it's not a story of missing out on a higher NA or shorter wavelength is fatal.

But you don't have to continue buying if you get what I mean? Unlike with DRAM where the same fab and same tools will make 1x, 1y, 1z, 1alpha, 1beta, etc... Foundry fabs are built with 1 or at maximum 2 processes in mind and they run those technologies forever. And when it comes time for a new technology, a new fab is always built. So the tool mix for a A14 or 14A fab will not be constrained by what EUV mix was used at N7/i7, or N5-N3/i4-i3.

Multipatterning efficiency will improve, this will help DUV as well.

Yes. But so too will direct print technologies as high-NA productivity marches along with low-NA advancements, and MOR improves all EUV technologies. My point was mostly that every technology has its place and there isn't a one size fits all solution. Not all lowNA EUV, not all highNA EUV, not all DUV. Using history as my guide, a mix of all the above will carry the day seems like the most likely outcome.

 

[Fred Chen]

If you have an EUV machine, it is because your specifically bought it and needed that capacity based on the number of EUV layers and the wafer starts. My argument here is that if people are doing things that could be done with DUV double patterning, it is because the total wafer cost went down (even though litho exposure costs went up) or the cost is close enough that the cycle time and or design EOU offered a better TVO.

My point was mostly that every technology has its place and there isn't a one size fits all solution. Not all lowNA EUV, not all highNA EUV, not all DUV. Using history as my guide, a mix of all the above will carry the day seems like the most likely outcome.

Our knowledge of EUV is always growing. Earlier on much less was known, so we can expect a fast buildup of an EUV fleet without knowing any better, and using them maximally, at least to get as much key data as possible. But now I expect people to be more careful. Especially with the newly learned non-optical aspects of EUV, such as electrons rather than EUV light actually defining the exposure, not to mention the plasma in the EUV machine etching the resist and blistering the surfaces.

 

[IanD]

I mean yeah. But you say that as if there will never be any situations from now till the end of time where high-NA will ever be more cost effective than low NA. Intel has said time and time again they will ONLY pull the trigger if it is the best PPAC path and that based on the data they see, that this cost crossover occurs in the 14A timeframe. TSMC agrees since they will use it on A14P. Unless you believe A14P will be a PPAC regression over A14 your comment doesn't agree with the public statements of either of the experts.

And what example do you have for that?

You're misunderstanding what I said -- I specifically meant for this node (A14), and at this stage in the cost/maturity of high-NA, and given the rate at which the new machines can be manufactured. Which matters much more for TSMC than Intel given their fab/customer volumes and ramp-up rate for leading-edge technologies. More specifically, the issue is that even if PPA favours high-NA (does it, at this node) it looks like C doesn't (for A14 at TSMC) -- though this will change in future as high-NA throughput/yield/cost improves.

Given that Intel are smaller volume and place a higher priority on performance and TSMC are bigger volume and place a higher priority on cost and area and yield and ramp-up rate-- all relative, not absolute! -- it's quite possible that high-NA is the right option for Intel at 14A, and also for TSMC half-a-node and a year later for A14P -- even though it's not for A14. It'll be some time before there are enough high-NA machines available from ASML to meet TSMCs high-volume needs, and that may well be what is slowing down their adoption compared to Intel.

As an example of Intel trying to do the "my process is the best in the world and *much* better than yours" and coming unstuck -- well, that'll be 10nm then... ;-)

 

[nghanayem]

You're misunderstanding what I said -- I specifically meant for this node (A14), and at this stage in the cost/maturity of high-NA, and given the rate at which the new machines can be manufactured. Which matters much more for TSMC than Intel given their fab/customer volumes and ramp-up rate for leading-edge technologies.

Ah I see what you mean now.

More specifically, the issue is that even if PPA favours high-NA (does it, at this node)
it looks like C doesn't (for A14 at TSMC) -- though this will change in future as high-NA throughput/yield/cost improves.

Litho doesn't give PPA though. Anything I can do with highNA I can after all do with a Hg arc lamp and A LOT of pitch division. It just won't be cheap or high yield. So if Intel thinks highNA is right for them then it has to be because area cost or design ease of use is better. Performance can't play any aspect of the discussion because at the end of the day the transistors and their electricals don't care how the features were patterned. Just that they were.

Given that Intel are smaller volume and place a higher priority on performance and TSMC are bigger volume and place a higher priority on cost and area and yield and ramp-up rate-- all relative, not absolute! -- it's quite possible that high-NA is the right option for Intel at 14A, and also for TSMC half-a-node and a year later for A14P -- even though it's not for A14. It'll be some time before there are enough high-NA machines available from ASML to meet TSMCs high-volume needs, and that may well be what is slowing down their adoption compared to Intel.

I don't fully buy this line of logic based on how long into the future A14 is and how few tools are needed if you are only doing a select few layers. I think it is just TSMC measuring out their risk, because a process slip at this juncture would be cataclysmic to TSMC's current market position.

As an example of Intel trying to do the "my process is the best in the world and *much* better than yours" and coming unstuck -- well, that'll be 10nm then... ;-)

But nothing about 10nm that I can see was ever about style over substance? Intel had a target and they tried as best as they knew how to meet the target. It was done, but it took longer than expected and by the time it worked out it was obsolete. A botched job doesn't really strike me as invoation for the sake of saying "look how cool we are" without devoting a thought to practicality. But maybe I misunderstood your intent since you are talking about going from stuck to unstuck in your second post, rather than talking about style of substance.