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Hi,
It just popped over my mind what will be the power consumption impact during soft reset is set by s/w for long duration and not clearing it.
Some of our IPs use the soft reset pin OR'd with power on reset and it will hold the reset pin of all the flops till software clears this bit.
All the clocks will be running so i am worried on the power consumption impact in cases where the s/w doesn't clear this bit immediately?
We are targeting SoC and for power estimation we use the PTPX during post layout. Haven't tried PowerArtist yet. However i was wondering if any of you faced such scenario.
Satya,
You may need to ascertain from the IP designers if they are gating the clocks on the flops when at reset, and how the flops are getting reset. Gating of flops is one method used by designers to save power.
Regards
Why would the SW keep soft reset in set state for a long time? If this is just a thought and you want to analyze it, you can always create a VCD and pass it to PTPX for this period and collect power numbers. If clocks are toggling, the ckt will experience quite high power (Dynamic + Leakage). If such a case needs to be avoided in hardware the designer may want to gate clocks or if the period is quite long and power domains are defined, you may even plan to turn off the circuit.
If the controls from HW are available, it is highly likely that SW will try to minimize power by programming relevant bits.
Just to reinforce Gauravjalan's feedback, getting a VCD from the reset period and read it in PTPX is probably the most straightforward approach. Experience also showed me that it is a good practice to verify that reset state of the flops is properly modeled in the .lib files regarding power consumption (either by having a look directly in some .lib files or by correlating with SPICE simulations for two or three flops).
Hi Satya,
As long as the flip-flops are properly characterized in the Liberty file (with both internal power and leakage being state dependent), you should be able to accurately measure the impact of the soft reset which is not properly deasserted, even at RTL. If the amount of wasted power is high and if you believe there is a risk this scenario may occur in the real application, it is possible to introduce safeguards in the hardware. As explained by Venkataraman and gauravjalan, this can consist of introducing clock gating. You could use the reset signal as a condition of course but it is probably better to use self gating techniques (with XOR or OR gates) which could also reduce power outside of reset. Performing a differential power analysis on the modified RTL should help in deciding if the newly introduced optimizations are actually worth it (there is basically a compromise between reduce dynamic power and increased leakage). Hope this helps.
Best regards.
