Daniel Payne
Moderator
Web event: STMicroelectronics: Successful Last-minute Functional ECO Implementation with Formality Ultra
Date: February 5, 2015
Time: 10:00 AM PST
View attachment 13160
Duration: 60 minutes
STMicroelectronics describes how they used Formality® Ultra to meet their tight release schedule for their ARM® core based designs despite having to implement multiple functional ECOs late in the design cycle.
Some of the ECO changes were previously impossible to implement manually but with Formality Ultra, they were able to implement the changes and still meet their tight schedule. Synopsys will give a brief overview and discuss the latest enhancements that help speed functional ECO implementation and verification using Formality Ultra.
Speakers:
Kailash Digari
Group Manager CPU-GPU design, STMicroelectronics
Kailash Digari is a Group Manager of the CPU-GPU team with STMicroelectronics in Greater Noida, India. Kailash has over 15 years of experience in the VLSI industry, and has worked in various roles including specifications, design, front-end and DFT flows, and product delivery. Kalash has experience in FPGA architecture definition, ultra-wideband SoC development.
John Lehman
Senior CAE Manager for Formality, Synopsys
John Lehman is the Senior CAE Manager for Formality at Synopsys. John has over 25 years of experience spanning the areas of ASIC design, software development, simulation, modeling, synthesis, and formal verification. Prior to Synopsys, John held technical and management positions at Mentor Graphics. John received his BSEE from the University of Portland.
Register Online Here
Date: February 5, 2015
Time: 10:00 AM PST
View attachment 13160
Duration: 60 minutes
STMicroelectronics describes how they used Formality® Ultra to meet their tight release schedule for their ARM® core based designs despite having to implement multiple functional ECOs late in the design cycle.
Some of the ECO changes were previously impossible to implement manually but with Formality Ultra, they were able to implement the changes and still meet their tight schedule. Synopsys will give a brief overview and discuss the latest enhancements that help speed functional ECO implementation and verification using Formality Ultra.
Speakers:
Kailash Digari
Group Manager CPU-GPU design, STMicroelectronics
Kailash Digari is a Group Manager of the CPU-GPU team with STMicroelectronics in Greater Noida, India. Kailash has over 15 years of experience in the VLSI industry, and has worked in various roles including specifications, design, front-end and DFT flows, and product delivery. Kalash has experience in FPGA architecture definition, ultra-wideband SoC development.
John Lehman
Senior CAE Manager for Formality, Synopsys
John Lehman is the Senior CAE Manager for Formality at Synopsys. John has over 25 years of experience spanning the areas of ASIC design, software development, simulation, modeling, synthesis, and formal verification. Prior to Synopsys, John held technical and management positions at Mentor Graphics. John received his BSEE from the University of Portland.
Register Online Here