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Hierarchical Monte Carlo analysis at DAC

Daniel Payne

Daniel Payne

Moderator
Memory designers have long used Monte Carlo analysis as a technique to understand their bit cell robustness to process variations, and help to optimize transistor sizing. There's a brand-new GUI available from MunEDA to enable hierarchical Monte Carlo analysis, now being shown at DAC in San Francisco. This looks to be a real time saver for memory circuit designers.
View attachment 14505
 
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