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OK, just read the article at https://www.anandtech.com/show/14758/hot-chips-31-live-blogs-cerebras-wafer-scale-deep-learning, where it shows die mounted to a substrate, now that makes sense.
Cerebras used a TSMC 16nm process, but somehow they worked to increase the reticle size beyond 32mm x 26mm to fill an entire wafer, or it's likely that they did multiple exposures at the maximum reticle size. I really haven't heard of other fabs doing full-wafer chips because the yield...
Arthur, we have to wait for Cerebras to disclose more details at the Hot Chips conference, so this is quite the accomplishment to actually get yield on a 16nm Wafer Scale Integration (WSI) project. At Intel there was research into WSI going back to 1978, but the equations predicted that you...
Yeah, the largest wafer-scale chip on the planet award goes to Cerebras at 1.2 trillion transistors. Aimed at speeding up ML operations, this is outrageously interesting. In theory as a die size increases the yield should approach zero, so how did Cerebras and TSMC team up to create this mammoth...
21st ISQED - March 25-26, 2020 - Santa Clara Convention Center, California
About the Conference
A pioneer and leading interdisciplinary conference, the 21st International Symposium on Quality Electronic Design (ISQED2020) accepts and promotes original and unpublished papers related to the topics...
Arthur,
There's an entire industry already formed around "medical alerts", here are the top 10 devices, https://www.consumersadvocate.org/medical-alerts/a/best-medical-alerts
Many seniors are phone-phobic, so getting them to actually use a smart phone is a barrier...
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Arthur, I listened to a radio episode talking about that poker-playing AI system this week, but remember that AI today is totally domain-specific, meaning that there is NO general purpose AI out there. Yes, AI and specifically Machine Learning is used in many places of EDA tools, just click the...
21st ISQED - March 2020, Santa Clara Convention Center, California
Submission Deadline: Sept. 14th, 2019
About the Conference
A pioneer and leading interdisciplinary conference, the 21st International Symposium on Quality Electronic Design (ISQED2020) accepts and promotes original and...
Submission site for extended abstracts is open; other submission sites to open August 6, 2019
Louisville, CO—July 9, 2019 —The 2020 Design and Verification Conference and Exhibition United States (DVCon U.S.), sponsored by Accellera Systems Initiative, announces its call for extended...
Great question, and at least DARPA has been looking at securing the IC parts supply chain.
https://gcn.com/articles/2019/01/14/darpa-supply-chain-security.aspx
Call for Papers
ASP-DAC 2020
http://www.aspdac.com
January 13-16, 2020
China National Convention Center (CNCC), Beijing, China
Aims of the Conference:
ASP-DAC 2020 is the 25th annual international conference on VLSI design automation in Asia and South Pacific regions, one of the most...
Call for Papers
21st ISQED - March 2020, Santa Clara Convention Center, California
Submission Deadline: Sept. 14th, 2019
About the Conference
A pioneer and leading interdisciplinary conference, the 21st International Symposium on Quality Electronic Design (ISQED2020) accepts and promotes...
It's just a matter of time before the Chinese government starts to add US Vendors to their own blacklist as a form of retaliation. Back in 2016 my youngest son purchased a Chinese smartwatch on eBay, only to discover that it was sending all of his phone contacts to China, quite the privacy...
R. Iris Bahar to Receive Marie R. Pistilli Women in Engineering Achievement Award
Brown University professor honored for outstanding technical contributions in energy efficient and reliable electronic systems, nanoelectronics, and nanotechnology
LOUISVILLE, Colo. – April 24, 2019 –– Iris...
Scope broadened to include embedded software. Calls for papers, tutorials and panels issued.
Munich, Germany – March 21st, 2019 - The Design and Verification Conference & Exhibition Europe (DVCon Europe), sponsored by Accellera Systems Initiative, has announced the call for papers, tutorials...
2019 IEEE International Conference on Modeling of Systems Circuits and Devices
Organised by Joint Chapter of CAS /ED Societies, IEEE Hyderabad Section
2nd MOS-AK India Conference (IEEE Conference #45395)
Venue: IIT Hyderabad February 25-27, 2019
The MOS-AK Compact Modeling Association, a...
Lattice Semi a turnaround story? Shares at highest point in 15 years - oregonlive.com
Lattice is the third, but smaller competitor to Xilinx and Intel in the FPGA market.
