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  1. J

    Intel splits Foundry from Design

    My understanding is that Intel won't be able to monetize Fabs 12, 22, & 32 until they finish rolling out the 12nm process that they're codeveloping with UMC. They quoted a 2027 date. The current processes on those fabs are only set up for internal use. They're not available nor set up for IFS...
  2. J

    Samsung Reportedly Scrambling To Boost 3nm GAA Chip Yields, Which Are Said To Have 20% Yields

    I've read articles regarding why i10nm failed. It would be interesting to read something detailing why Samsung's hasn't been able to get GAA off the ground. I speculate that they were too ambitious, like Intel was with their original i10nm. They just tried making too many changes at the same time.
  3. J

    Samsung Reportedly Scrambling To Boost 3nm GAA Chip Yields, Which Are Said To Have 20% Yields

    Poor Samsung, their lack of success with GAA node is quickly becoming their version of Intel's original 10nm node.
  4. J

    Shared pain shared gain: the start of a monopoly in leading-edge logic chip manufacturing ?

    Thanks for the link. I ChatGPT'd the question “is TSMC's dominance of the fab market a possible antitrust case?” and the response I got was so convincing, I felt like there was zero chance at the moment of any antitrust, as you commented.
  5. J

    Shared pain shared gain: the start of a monopoly in leading-edge logic chip manufacturing ?

    True, we can't blame other companies' incompetence/bad luck for TSMC's success. I'm obviously out of my area of expertise. I had a thought that it maybe a future case of antitrust, but, after reading a little on the topic. There is no case for it.
  6. J

    Shared pain shared gain: the start of a monopoly in leading-edge logic chip manufacturing ?

    That's not what I was talking about. I meant competition at the leading edge: where a company like Apple could go to TSMC vs. another one and actually have an option. A decade ago or so, companies could do something like that. You could go to Samsung for 14 nm vs. TSMC for 16 nm. Now, there is...
  7. J

    Shared pain shared gain: the start of a monopoly in leading-edge logic chip manufacturing ?

    TSMC and ASML are almost like a type of duopoly. If the USA didn't have the issues it has with the PRC, SMIC or whoever would be a good counterbalance to TSMC's domination of the leading edge.
  8. J

    Moor Insights: “[if] you spin out IFS before Design & IFS is healthy, it will fail”

    I can't see Intel dropping its 18A process at the stage where it's at compared to GF's aborted/abandoned 7nm process node. So whatever happens next will be fascinating.
  9. J

    Intel indicating Arrow Lake will not have a 20A version

    They only have or only will have one fab making all three nodes ("4, 3... 18A in 2025...")?
  10. J

    TSMC’s 3nm & 5nm Processes Expected To Generate Over $31 Billion in First 3 Quarters

    Don't you think that spinning off the manufacturing division would appear more like a negative move, as it could be perceived as a sign of failure by the market?
  11. J

    "Intel Years From Success in Foundry Business, Analysts Say" “The yields are just really bad,” Bernstein Research senior analyst Stacy Rasgon told EE

    That's how some people have characterized it or that Intel 3 is at best like a half-node).
  12. J

    TechInsights: Introducing TSMC N3E As Seen In Apple M4 SoC

    Thanks for the highlights. Have you tried doing a summary of an article with ChatGPT or Claude for the main points?
  13. J

    Tokyo Electron Launches Acrevia™, a Gas Cluster Beam System for Ultra-Fine Patterning in EUV Lithography

    https://www.tel.com/news/product/2024/20240708_002.html Tokyo Electron Launches Acrevia™, a Gas Cluster Beam System for Ultra-Fine Patterning in EUV Lithography Tokyo Electron (TEL; Head Office: Minato-ku, Tokyo; President: Toshiki Kawai) today announced the launch of AcreviaTM, a gas cluster...
  14. J

    Tokyo Electron Launches Acrevia™, a Gas Cluster Beam System for Ultra-Fine Patterning in EUV Lithography

    https://www.tomshardware.com/tech-industry/tokyo-electrons-new-tool-can-reduce-the-necessity-for-euv-double-patterning-and-improve-yield
  15. J

    Rapidus Set to Open 2-nm Pilot Fab, CEO Says

    The Japanese have some defense law or rule about producing some things in Japan (e.g., high price ticket items in the defense industry like tanks, jet fighters in the past, transport aircraft, submarines). They do this even if the product costs double or triple if it had been imported. I wonder...
  16. J

    The Final Nail in Intel’s Coffin?

    ARM posted info on the "X5" yesterday, which they named the Cortex-X925. https://newsroom.arm.com/blog/armv9-cpus-consumer-devices
  17. J

    The first Russian 350nm lithograph is being tested

    Wow. The Russians achieved something the USA did back in 1995, nearly 30 years ago. https://en.wikichip.org/wiki/350_nm_lithography_process
  18. J

    The Technology Gap Between Leading Western and Chinese Semiconductor Foundries

    It's nice to see they are investigating alternative approaches to EUV. We need more options. Competition is good for all.
  19. J

    Declining density scaling trend for TSMC nodes

    Thank you. N10 vs. N7 would be closer to 2x; and A14 vs. N5 might or might not reach 2x, but it's all speculation at this point.
  20. J

    Declining density scaling trend for TSMC nodes

    It would be interesting to do a trend plot comparing nodes every 3 or 4 years rather than yearly; and see how much it changes. How close do they get to 2x performance?
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