You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!
Exactly. I am drawing the line at 45nm, as I said, when a .7x reduction of size stopped for gate oxide thickness and introduction of high-k/metal gate to get a factor 2 reduction in surface and the at the same time a factor 2 in the other parameters was required. Strain at 90nm did not involve...
Guys, back to the basics please.
Device engineers knew all along that Dennard scaling was ending, it was designers that wouldn't listen.
Dennard formula, based on the physics of the basic CMOS structure, was indicating clearly what was being gained by reducing the size of the devices. Its beauty...
Because you need a lot of land, a huge amount of water and electricity and a good transport network. Some places that may look good cannot provide the water or electricity without disruption to the local economy, or the land is already at a premium. Workforce is mobile and if you have to pay...
Liquid cooling using water in HPC and datacenter racks are already a standard technology. The blades have the integrated radiators with piping and you can even replace blades without cutting the water supply. The overall heat extracted can then be injected in climatisation or other energy saving...
All is in the proportionality of the different variables. Reducing size typically increase R, C is a strange beast and depends on materials and topology, at that point you rely on I increasing enough to compensate. Vertical symmetry bring you nothing at device physics level compared to...
Two factors having me doubting the vertical FET (and this has been for years...).
1) at the end of the day the problem of density in logic (VNAND is a different structure) is how to place three contacts on a plane and
2) how to have a W that allows enough current to drive the line at the L you...
If you for something more scientific I suggest the link between volumes and process control. TSMC has been consistently capable of aggregating enough volume of processed wafers in R&D and early ramp-up to make process control and yield feasible. Do not forget that variance goes as the root...
Daniel, the usual problem as with the "Airbus of chips" in 2012.
On one hand you have the EU Commission, who sees the strategic weakness of not having advanced node capabilities in Europe but hasn't the political power of pushing for TSMC or Samsung to set up shop here. So it tries to have the...