Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/search/294624/?c%5Busers%5D=SPQR54&o=date&page=2
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2021770
            [XFI] => 1050270
        )

    [wordpress] => /var/www/html
)

Search results

  1. S

    Semiconductor R&D spending by company

    When you compare you have to take into account that for IDMs you have both process and product development spending, fabless only product and foundries only process.
  2. S

    China hits back in the chip war, imposing export curbs on crucial raw materials

    Gallium is present in bauxite at 10g to 150g per metric ton. By comparison Al is about 250kg per metric ton of bauxite. The real problem is then the extraction process from the byproducts of Al mining. Very dirty process with a relatively low yield. Some are looking into it as it can be a way...
  3. S

    Primary contributors to wafer fab cycle time (which process steps?)

    A well run fab has no bottlenecks in front of litho, it is build to have uniform throughput and you do not buy one tool more or less than necessary to maximise overall use. Underinvesting and creating bottlnecks is very quickly anti-economic and you do not have more or less depo/etch/clean...
  4. S

    Samsung Planning Semiconductor Plant in Europe?

    STM is very much Franco-Italian. Minority blocking stakes are still in equal measure with the two Governments. And, depending on the market segment one focus in, it can be perceived more French or more Italian. A lot of "lost in translation" issues with the piece that makes a big confusion of...
  5. S

    Primary contributors to wafer fab cycle time (which process steps?)

    300mm wafers move from tool to tool in standardised FOUPs (Front Opening Unified Pod) usually of 25 wafers (may be 13). Production is really a batch process even if some tools are single wafer processing. So indeed you have time spent to serialise the process and then parallelise the transport...
  6. S

    Intel's Conflict of Interest? Can it overcome TSMC

    AMD to GF all over again, but without Mubadala money ? Who is going to pay for IFS while it gets customers, Intel? If so why spin off and why customers should believe they will be treated on an equal footing. If not, where is the money to keep going and stay in the development race until it...
  7. S

    EU Chips Act likely to get green light on April 18 -sources

    Details are not out yet. But there is a major difference between the two. In the US you have a central government taking the decisions and handing out the money. In EU no money from the Commission for the production initiatives (only R&D) and each member state will be able to support the...
  8. S

    How thick is the water film in 193i?

    Seen only now. There are multiple considerations for choosing thickness of water in an immersion stepper and not all of them purely due to the lenses. Just to name two of them, you need the flow of the water to be laminar otherwise you have distortions due to turbulence and you need the water...
  9. S

    Intel Wants $5 Billion More From Germany for a Chip Plant

    It started as AMD and become GF later, but all the bulk of the investments (AMD and GF eras) were during the period of relaxation of EU State Aid limitations for former East Germany. Now Germany cannot give out the same conditions as that transition period is over. Any subsidy now need...
  10. S

    The viability of CFET alternatives?

    Scotten, one lesson I learned with monolithic 3D is that a good technological solution doesn't get picked up if it doesn't cover all the spectrum of products. If can only do SRAM and not general purpose logic is a no go. One of the option we looked into with monolithic 3D was to put all the SRAM...
  11. S

    What does the semiconductor shortage mean for Europe?

    Daniel, you and other reporters should spend a bit of time really looking into the announced EU Chip Act, start separating facts from fiction and do not take press releases as a reliable source of information. Everybody talks about 45B€ without reading the relevant, public, official papers and...
  12. S

    Intel may have second thoughts about the new fab in Magdeburg Germany

    In Europe only Intel, ST and GF have fabs for nodes below 90nm. All other 300mm fabs (IFX and Bosch) are for equal or larger geometries devices. It is the reason why IFX, Bosch and NXP are rumored to be those trying to get TSMC here (no A-grade source there either ....). Would like to be the fly...
  13. S

    Maskless lithography

    Agreed that is doable, my point is that requires a lot of engineering resources to do it, as there are a lot of challenges that make it a risky development. And this for an even smaller market that existed before EUV. I have not really looked into it since the demise of Mapper but I am not aware...
  14. S

    Maskless lithography

    One of the issue with multibeams technology is that wafer throughput is also linked to the bandwidth of the transmission of data to the writing head. When you workout the numbers you see why is used for masks but not for wafers. Also, as one of my more experienced colleague told me many years...
  15. S

    The viability of CFET alternatives?

    Never forget physics. In CMOS you want a well behaved switch and this impose a lot of constraints for electrostatics. When you look at nanowires/sheets, regardless of their orientation in space, you have some critical dimensions you cannot ignore so there are limits (lower and upper) for the...
  16. S

    The viability of CFET alternatives?

    The flow has some process steps similar/common with that proposed by CEA-Leti for the monolithic 3D (that by the way was partly generated by the idea of putting the SRAM on top of the logic as it was going to stagnate in density at some point). And one of the objections by foundries was that in...
  17. S

    PSMC CEO oppose Taiwanese version CHIPS act

    Powerchip is PSMC since 2018. Photronics Taiwan was rebranded PDMC when they struck the deal with DNP in 2014 and, if the company is still the same I knew, they didn't pay for one more day that necessary for the ownership of the acronym. ;)
  18. S

    Affect of the European Chips Act on the wafer size trend in Europe

    The survey represent the view of the current demand side in Europe. As there is no more consumer digital the view is is relatively narrow and is one of the sources of lack of understanding among the actors. At macroeconomic view, EU consumes as much advanced digital as the US, it is just that it...
  19. S

    Affect of the European Chips Act on the wafer size trend in Europe

    Government role is only one element. TSMC and the Korean memory manufacturers would not be where they are without the state and bank aid they got between 2000 and 2010, when they were building capacity and pushing competitors and IDM out of the maket thanks to access to capital and tax...
  20. S

    Affect of the European Chips Act on the wafer size trend in Europe

    If you look at current announcements you can see that investments are planned at both sizes depending on economy of scale. Bosch has done a 300mm fab in Dresden for old BiCMOS technology for capacity, ST/GF will invest together in 300mm in Crolles for FDSOI 22nm and below, ST/Intel...
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