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Not much surprise here - except perhaps a bit of shock that editorial departments might prefer to report news excitably. Corporate restructurings, layoffs, right-sizing and other activities that cut employment are regular business activities. During tight economic times, companies will also use...
I understood that the question was if 3D designs being applied to memory could be applied to 'other' aspects - which would seem to be more than adding layers on top of logic chips. Thermal issues related to intensive logic circuitry (already having thermal issues) will obviously increase as...
Here are a few other references one might want to look at to see detailed analysis of the thermal experiences of vertical interconnections.
The Development and Progress of Multi-Physics Simulation Design for TSV-Based 3D Integrated System - https://www.mdpi.com/2073-8994/15/2/418
Heterogeneous...
Vertical inter-tier vias provide well documented thermal advantages.
Stacking many layers of logic does cause thermal issues, but again you want to balance design with objectives.
Cliff - funding information would be confidential and I would not be posting on a (semi)public site. ;-)
You can...
Layering technology employed by Mircon is not unique. Massively deployed Monolithic inter-tier vias are something we are investigating for our new low latency, low power data switching platform. Designed around data arrays rather than embedded logic, we are quite excited about the scalability of...
What is the highest number of pins you have seen on a package.
Network switch chips would seem to have the highest number. Am presently researching the limits of packaging.
https://www.servethehome.com/massive-64x-400gbe-intel-tofino-3-switch-chip-at-vision-2022/
