TSMC statement on next-generation EUV

[hskuo]

Valid input. But for what’s worth intel said 14A was 2 years after 18A so intel has 2 years rather than 1. It is also is worth baring in mind this is a far smaller labor from ASML than EUV was. As a result I have to assume there is comparatively little uncertainty around the tool’s capabilities.

Bingo. If A14 was lacking high-NA I think there would be a stronger argument that intel wants to jump the gun too early. But as you pointed out N2 family is just coming out too soon for this to make sense, with a retrofit making even less sense. But in the meantime I have no reason to believe that they won’t since TSMC stated that they think it would be more economical. I would never claim to be a litho expert, but I would bet on 2 major logic houses and Scotten over the uncertainties we might have.

Agreed. I just don’t make assumptions around others failing. So it is just perplexing that I see all the talk of how intel is destined to have made the “wrong call”, but TSMC making the same claim is somehow a rejection of intel’s theory and is objectivity the “correct” move. My personal philosophy is that assuming competitors can’t do what they say they will is a great way to fall behind. This is especially true when all three of the logic houses are as fearsome as they are.

Why would that constitute a hint? Wouldn’t intel always want to move to larger reticles if they have made the choice to go to high-NA? Even if high-NA was 50% the cost of EUV SALELE instead of the 90% that Scotten projected in his article, you would always want to go to that larger reticle to get costs even lower. If someone doing a reticle sized die is using IF then they would also no longer need to worry about stitching which is a cost improvement for the foundry and the customer who now needs less work/fewer masks. If I was to pick any evidence of intel leaping before looking it would be announcing the intent to use high-NA before even having their first development scanner up. Either way it is incomprehensible that from mid level lithographers/intergrators, to Mark, Ann, and then Pat didn’t do their due diligence before deciding that high-NA would be valuable to the 14A program. If a decision that big can go through the whole chain without good feasibility studies I have genuinely no clue how intel lucked into figuring out how to fix 10nm or how to ship intel 4/3.

I thought you are not so familiar with Hi NA EUV scanner and the challenges. Hope I am wrong. If it is smaller labor in HNA EUV comparing to low NA EUV, then there will be no stupid user to pay 2x more price for the new tools. If you think ASML is monopoly to control the adoption, it is not that easy without demonstration of cost advantages which can not be validated now due to HVM tool is not ready yet. Besides, the HiNA EUV infrastructure is still under developing and takes time. If we retrospect the low NA EUV history, intel used to be the leading company in the early development stage. Hope the history will not repeat it again.
I can understand why Pat G made decision of adopting Hi NA EUV early. If intel wanted to take the technology leadership back by 2030, there are not many moves to take and Hi NA EUV is just few one of them. Super Via, BSPDN, advanced package technologies and STCO are some of them. The situation is the road ahead is bumpy but intel chooses to speed up now.
For reticle size argument, you might need to spend sometimes to know more technical requirements and limits.

 

[Xebec]

I have genuinely no clue how intel lucked into figuring out how to fix 10nm or how to ship intel 4/3.

I've been thinking about the Intel 10nm problem lately.

I would like confirmation on this, but I think after seeing a recent tweet (from Fred Chen?) it goes as follows:

- Intel went for 2.7x density via quad patterning (SAQP for some steps) to keep cost per area/transistor scaling downward vs 14nm.
- This large jump meant even more complexity and engineering work on top of the "increasing exponent" that each new node already brings
- Intel also ran into reliability problems with a materials choice (Cobalt) as proven with Cannonlake.

I understand the final Intel 10nm / "Intel 7" is significantly different than the original 10nm intended, which means the engineers threw out the Cobalt and went for more interim shrink to get significant yields with Icelake and finally Tigerlake (~ 2021).

FWIW, maybe related - Jim Keller was at Intel from 2018-2020 and talked about a time where the "Moores Law engineers" had given up on scaling, so he did an exercise to challenge them (in two weeks) to come up with a roadmap for 100x scaling. They got to 50x, and he gave them one more technique for another doubling. I don't know if this was the turning point but I like to think that he probably had some influence on Intel's engineering team looking into new solutions around this time. IIRC, It was either this interview:

, or another one with Ian Cuttress where he talked about this.

 

[nghanayem]

I've been thinking about the Intel 10nm problem lately.

I would like confirmation on this, but I think after seeing a recent tweet (from Fred Chen?) it goes as follows:

- Intel went for 2.7x density via quad patterning (SAQP for some steps) to keep cost per area/transistor scaling downward vs 14nm.
- This large jump meant even more complexity and engineering work on top of the "increasing exponent" that each new node already brings
- Intel also ran into reliability problems with a materials choice (Cobalt) as proven with Cannonlake.

I understand the final Intel 10nm / "Intel 7" is significantly different than the original 10nm intended, which means the engineers threw out the Cobalt and went for more interim shrink to get significant yields with Icelake and finally Tigerlake (~ 2021).

No. The density was never relaxed and cobalt was never removed. If you look at any of the ADL or TGL mobile teardowns you will still see all of the CDs intel showed off in 2017 and all of the headlining features are still there. But I will leave the actual enhancements that are easily visible at that since I don’t know what stuff techinsights has freely available and what needs which subscriptions. If you have a subscription the microscope shots they have make it easy to see the performance enhancements intel claims to have implemented.

As a side note it is really cool being able to see teardowns of CNL, all the way through to ADL.

 

[Xebec]

No. The density was never relaxed and cobalt was never removed. If you look at any of the ADL or TGL mobile teardowns you will still see all of the CDs intel showed off in 2017 and all of the headlining features are still there. But I will leave the actual enhancements that are easily visible at that since I don’t know what stuff techinsights has freely available and what needs which subscriptions. If you have a subscription the microscope shots they have make it easy to see the performance enhancements intel claims to have implemented.

As a side note it is really cool being able to see teardowns of CNL, all the way through to ADL.

Thanks for clarification!

 

[fansink]

In the past 15 years Intel spent precious money in share buyback program, dividends, and the infamous "contra- revenue" gimmick, there's no deep pocket left for Intel.

Intel needs to sell more products to maintain revenue and improve its cash flow, no matter the products are made in house or by external foundries. Intel Foundry's revenue and profit (if any) won't be big enough and quick enough to help.

Intel’s financial headwinds will not likely be easing any time soon.

Intel’s Free Cash Flow (FCF) is getting deeper in the red, with the bottom estimated by Intel to be around 2027.

Currently Intel’s TTM FCF is -14.3B, which has steadily dropped from +21.4B in Q420.

 

[Daniel Nenni]

Daniel:
1. I membered tsmc started N7 without EUV, but Samsung used EUV in SF7.
2. IMO, IFS is with high probability to lose big money for a long period of time and hope intel has deep pocket and always injects fresh blood to save the life. Because
a. Historically, it takes at least 2-3 years to win a big customer from engagement to ramp, to HVM. If 14A will be HVM ready in 2026 and everything will be executed
precisely and successfully, I would expect the tipping point will be after 2029.
b. In catch-up mode and as follower, it will need 10~20% die price lower as switching cost. As we all know, manufactured in US might have ~20% wafer cost higher
than in Taiwan. If tsmc's N2/A16/A14 GM is ~40%, then intel could start from GM 10~0% if the D0 is comparable and use the same EUV tools as tsmc. It is quite
challenging. Now intel bets on more expensive and not HVM ready HiNA EUV scanner. Intel needs not just deliver 14A on-time, but superfast yield ramp.

I would not say it is impossible, but I think intel bets on the goal which has very high possibility of missing the tight schedule, too many uncertainties.

Right, it was Samsung 8nm that was aligned with TSMC N7. 8nm was a good workhorse node for Samsung. Still is probably. Like N7 for TSMC.

 

[Fred Chen]

Why would that constitute a hint? Wouldn’t intel always want to move to larger reticles if they have made the choice to go to high-NA?

It's a big rebuild for the High-NA system, so their current EXE would be a wasted evaluation. Maybe they are seeing the productivity pitfalls of mixing with conventional field systems. It's possible they are still anticipating some large GPU die not just processor chiplets.

 

[Fred Chen]

No. The density was never relaxed and cobalt was never removed. If you look at any of the ADL or TGL mobile teardowns you will still see all of the CDs intel showed off in 2017 and all of the headlining features are still there. But I will leave the actual enhancements that are easily visible at that since I don’t know what stuff techinsights has freely available and what needs which subscriptions. If you have a subscription the microscope shots they have make it easy to see the performance enhancements intel claims to have implemented.

As a side note it is really cool being able to see teardowns of CNL, all the way through to ADL.

Intel 4 removed cobalt, so that implies the problem. Maybe they're stuck with the cobalt for Intel 7 (?), that would be unfortunate.

 

[nghanayem]

Intel 4 removed cobalt, so that implies the problem. Maybe they're stuck with the cobalt for Intel 7 (?), that would be unfortunate.

Regardless of how robust the process is why would they keep it? Per intel’s data the R for Cu with a Co cladding is significantly lower than Co with only a tiny electromigration degradation. IMO that is a clearly better solution regardless of what intel could achieve with Co (doubly so as interconnects get finer). As for switching out your contact via/M0/V0/M1 metalization that sounds like a huge thing to change after the fact. Throw in SAPQ and the fact there is no fixed via grid like intel says they added for i4, and that makes screwing with that section of the flow sound really scary to me. Don’t fix what ain’t broken as they say.