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Just wondering whether we are entering post fabless era where SoC companies are not only outsorucing fab activities, but also outsourcing backend design activities and want to concentrate spec to RTL or spec to Netlist.
The fabless era has started when setting up of fab has become costlier and demands economic scale. Also fab process have become standardized which enables clear hand-off between fabless companies and fabs.
The similar thing is happening in the backend desing area. The EDA tool cost at lower geometry like 28 nm or 40 nm is exhorbtantly high for one company it is becoming a challenge to invest the amount. Particualrly for small and medium SoC companies are doing one or two design in parallel. This has created a need of service providers who can aggregate backend desings from multiple companies and can amortize the EDA tool cost across several customers. Also the design flow has become matured and the hand-off between front end and backend team is quite smooth. Moreover the service provider may have design flow set up and also matured as that has handled several tape-outs. Hence involving a third party service provider seems more viable business option for SoC companies particualry small and medium size SoC companies
Very interesting topic.
In around late 80s/early 90s, the semiconductor industry was hit with the crisis - the rising cost of fabrication. In hindsight, the response of the industry was going after a divergent strategy.
The first fabless appeared in mid 80s (I think it was Xilinx - not sure though). Overtime, the fabless model was established. It looks like that the rising cost of fabrication crisis will be back, once we are into the non CMOS processes or hit the Moore's law or deal with very small geometries. The solution, Backend outsource? - it is easy to outsource as the IP could be protected rather easily. Who knows in the next 10-15 years, it is an established model, just like fabless model. There will, however be IDMs. What will this be called - Frontless ?
We're already there aren't we? I worked at a start-up a few years ago. We did in-house analog design through to layout and our digital team wrote verilog RTL which was verified on an FPGA. We then shipped this off to a company in (I think) Arizona who did the back end stuff for us. Our budget simply didn't cover the back end flow.
Funnily enough, this cake can be cut in almost any way you wish. Design ownership can be independent of almost everything except the contract...
My fabless analogue and consulting company started about ten years ago without layout facilities, and we used a subcontracting company for the layout. Then there was a period we did the layout in house, and now we are contracting it out again. The first time around we needed the layout people to be local so we could physically work together, but this time around the combination of advancing tools and improved communications means we can do almost everything remotely.
We also had the cake cut the other way around - another fabless semiconductor company was short of specific skills that we had, so we did some circuit design work for them - and they did the layout (some for us as well!).
It's also perfectly possible for a fabless company to write the specification and subcontract the entire process (but caveat emptor - and you need to understand the limitations of the specification as a communications tool).
(From experience, I know that there are some digital designs that can simply be "thrown over the fence" and you receive a valid tape and whatever back. Given the concentration of tools in this area, I suppose the range of such designs is expanding; however, even in the digital world there would always be a hard core of hard designs where interaction is needed.
I agree, the concept is not new, it has been started in 2003-2004 itself. In fact there are several companies are involved in this. The challenge is to make the model more effcient. The required interaction between the RTL designer (from the customer company) and the physical design team (from the vendor company) is much more than communication required between a fabless company and a fab. Also changing the vendor is a challenge as any vendor who has done a chip for a customer has distictive advantage to bid for the physical design of next version of chip due to critical learning he has. This makes the customer locked-in to a vendor more easily.
So the the focus now will be in creating effective communication process, effective project management system which will define the winning of this model. Also another key challenge is managing the schedule of multiple projects. The vendor needs to use limited number of EDA tool license across multiple projects from multiple customers, hence who can optimize the design cycles of these projects more effectively will be able to amortize the EDA tool cost more and offer lower price to customer
The concept of backend contracting is not new, just like fabless took time to get established. The question is not to make models or communication efficient, the question is how the semiconductor industry configures itself and what are the drivers of those configurations. If the driver is to relax the backend constraint, say for profitability, than efficient and working models and communications will be there. Right now that is not the case.
1. High EDA tool cost - Design below 65 nm requires huge investment in EDA tools and it does not make economical sense for a small and medium size company to invest 100% on the tools. Vendors can amortize the tool cost across multiple customers hence reducing the SoC development cost
2. Expertise in EDA tools - The number of tools and complexity have increased substantially in lower geometry node. This has resulted need of specialized skill set and a small and medium SoC company who has limited number of tapeouts can not built the expertise in-house. A vendor will have experience in multiple tapeout and hence can provide more efficient solution
3. Engineer idle time - Lower geometry node demands experts in different areas like STA, DFT, DRC etc. One engineer can not master all the areas. Hence for a small company who has 1-2 SoC designs are goiing in parallel the idle time for engineers in high which in turns result in high cost of development. A vendor can have multiple projects running in parallel and they can use the engineering resoruces more easily
Johan Dijkhuis • As someone in RF / mixed signal IC design I consider the layout as much part of the design as the schematic (maybe even more). Probably every analog circuit can be ruined by a bad layout. However, for 100% digital circuits it might be easier as the tools will be able to estimate at least some of the nasty effects and avoid them.
