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On that specific note I would say it went down. As an example RF devices used to be on leading nodes but all else being equal smaller transistors give worse performance so those sorts of use cases eventually stopped moving to new nodes (at least as fast) as they hit a good sweet spot. And I have...
I could only hope this is true, and that this is true it was a worldwide issue. The larger the labor shortfalls get that would hopefully catalyze a change in how the semiconductor manufactures source their talent to be more inline with the rest of the chemical industry. And while it wouldn't...
That doesn’t change the point the Hskuo was making. Systems companies (besides Apple) weren’t making their own chips back in 2015. Google bought off the shelf SOCs for Pixel from merchant chip vendors. Cloud was not nearly as big as it is today and those folks were buying from AMD and mostly...
Fab engineers and techs aren't unionized at any company outside of maybe ST-M which I think recently went on strike or something like that. And since we no longer live in the 1960s they also have round the clock coverage. If union folks are headed home, those are construction workers. Now, maybe...
What is fantastical about it? The price of the tools don't double if the final destination is in the US vs anywhere else. All else being equal, sure the shell will be far more expensive, but I think that it could be not as bad as you'd think. As an example a fab in TW will need way more support...
I have two minds on this. Assuming you cut out all of the logic and memory IDMs, my understanding TSMC is the largest 2.5/3D packaging house (because my understanding is that OSAT 2.5/3D ecosystem is more rudimentary). On the one hand you may want to keep things locked down as that makes TSMC’s...
Regardless of how robust the process is why would they keep it? Per intel’s data the R for Cu with a Co cladding is significantly lower than Co with only a tiny electromigration degradation. IMO that is a clearly better solution regardless of what intel could achieve with Co (doubly so as...
No. The density was never relaxed and cobalt was never removed. If you look at any of the ADL or TGL mobile teardowns you will still see all of the CDs intel showed off in 2017 and all of the headlining features are still there. But I will leave the actual enhancements that are easily visible at...
Valid input. But for what’s worth intel said 14A was 2 years after 18A so intel has 2 years rather than 1. It is also is worth baring in mind this is a far smaller labor from ASML than EUV was. As a result I have to assume there is comparatively little uncertainty around the tool’s capabilities...
Why would anyone assume it is a bad decision. Intel wasn’t forced to adopt high-NA for 14A. They looked at the numbers and thought that this would give either the best cost or at worst the most reasonable tradeoff between cost and ease of use (something that presumably matters more for an...
I am almost 100% certain he has no contacts and no sources. The only correct thing I have ever seen fall out of his mouth is what you could have gotten from Wikipedia, a college textbook, and or a basic understanding of science/engineering. The data from his so called “team” or “sources” is...
Maybe lithogru had a mix up between i3 and 18A, because 14A is most definitely not part of 5N4Y and intel has said that 14A is when intel plans to go back to a relaxed 2 year cadence.
12FFC was to sweeten the lack of scaling between 16FF and 20nm in spite of the added cost. I would assume N6 is in a similar camp given the lower mask count from EUV adoption and that it came out after N5 was spinning up.
I am curious to see what this looks like once we see teardowns. Based on...
Not surprising. Even if TSMC isn't adopting it for production as fast as intel, they still need R&D tools to actually be able to one day adopt it.
TSMC said as much on their most recent call. But who knows maybe Dylan Patel and his totally not made up "sources" are smarter than...
I obviously can’t say for sure, but it seems like TSMC is relaxing interconnect pitch for A16. By going to BS contacts they don’t need M2 or M0 power rails. Just looking at TSMC’s tried and tested 6T HD cell, removing the two power rails should reduce cell height by 1/3. And unlike the intel 4 +...
This is kind of my point Dan. Originally I had assumed the negative talk around TSMC AZ was completely empty fear mongering from a small number of folks with an axe to grind and or instances of people not understanding that manufacturing (and not just for semis) is hard/high pressure work...
Yeah I wasn't super clear about that. It wasn't really a jab at technological competitiveness as that is a remains to be seen sort of thing given intel hasn't talked about what 14A brings over 18A and even then we need to wait until 2026 just to see how the different aspects of N2 stack up vs...
Kind of disappointing to hear that TSMC is doing two teams with 5-7 years of development. That would mean the earliest we can expect A14 (or I guess in light of the renaming of N2+BSPD to A16, that they are more likely to go with A12) is 2028, and worst case 2030. If TSMC lets the gaps between...
I have a lot of disorganized thoughts, so I will try to have them listed as coherently as possible:
Originally I had thought that the TSMC AZ stuff was way overblown, but there is too much evidence that I can no longer just write everything off anymore. There is clearly some degree of issues...
