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It's a long existing problem that the current pellicle cannot survive high power EUV illumination, it's unclear if ASML can solve this issue in 1-2 years, but they keep avoid talking about it as if the mask inspection tools can solve all the problems. A following question is how frequently an...
I guess you can mathematically do something like inverse transform to calculate what the exact wavefront at the mask surface should be to match your target pattern, but the problem is that both phase and intensity of thus calculated "mask" wavefront are continuous or analog signals (spatial...
Of course it's not only ppt, they reported some preliminary experiment results to show its feasibility. High-NA EUV is not the only path. Several different approaches to scale down exist, including SADP EUV (low NA) patterning proposed by Imec. Intel booked some high-NA tools. I heard TSMC did...
SPIE just published the papers from Advanced Lithography + Patterning. Here are a couple of pages, figures and table grasped from the 7x paper (see below) by Westlake University. Obviously, our industry should seriously think about if we really need high-NA EUVL. TSMC may again make a right...
This is only my opinion: if the metal pitch is in the middle of 40-28nm (say 34nm), the via alignment margin probably is still ok, but unlike TSMC that has not adopted SAV (they showed a upward SAV technique for top vias in 2021 IEDM) at 5nm node yet since they have EUV scanner to print much...
Sometimes they intended to say something to mislead people (including their own people). The practical paths seem to be: a) Keep BEOL unchanged (due to export control and the challenges to implement SAQP) at 7nm node level (metal pitch ~40nm) and replace FinFET with GAA NS to gain power and...
From what I know, their CFET study is on the very "conceptual" discussion, not even in the "pathfinding" stage. The real focus is still on GAA nanosheet and a refined 4-gate forksheet (keep it in mind that Imec's forksheet is a 3-gate device, not GAA). Intel and Samsung both also worked on a...
Huawei‘s money seems to be unlimited and possibly backed by Xi and his party. SMIC is a different story, it doesn't appear to gain the full trust and may only get certain level of support. Anyway, I think this is a different story.
The very-high volume products such as smartphones (e.g., iPhones) and non-AI PC are still allowed to enter China, but anything related with AI (such as nVidia GPU, including future AI PCs) and high-speed computing will be banned. What they lack are the cutting-edge chips for these banned AI and...
If we mainly consider the economy or yield of advanced-node high volume IC, yes, we can understand what's going on in Taiwan, US, etc., but won't understand what Huawei/SMIC is doing and why they are developing a desparate 7x patterning way to get around EUV. They fully understand their risks if...
It looks a lot of social news such as 知乎 about Huawei patents in Chinese local-net have been blocked (404, only a few produced by bigger media guys left). What do you think? This cannot be achieved by a simply private company, it's backed by party/government and the whole country's effort! It...
It is still on the early stage of process development. This paper reported some preliminary experimental results of a simplified grating structure using Ru (& direct metal etch), not a fully integrated detailed result, but good enough to show the potential of this technology, including a...
It should be available soon in SPIE digital library. Keep it in mind the multi-color self-aligned block (renamed by TEL and Imec) is actually self-aligned cut (dielectric)+metal filling (damascene), and the key idea of self-aligned cut is using different materials arranged in an alternating...
I am not clear about the TEL or Imec patents, apparently they had done a lot of follow-up work since 2017. Here are some references about single-material SAQP/SATP ([1-3]) for density multiplication and dual-material SAQP/SAMP for solving EPE issue [4-6]:
[1] P. Xu, Y. M. Chen et al., “Sidewall...
