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    by Published on 12-18-2017 11:00 AM
    1. Categories:
    2. Mentor Graphics,
    3. Tanner EDA,
    4. IoT Internet of Things
    Article: What Changed On My Transistor-Level Schematic?-pliny-min.jpg

    I recently was introduced to a white paper written by John Stabenow, Director at Mentor, a Siemens Business, that gave an excellent overview of things to consider before launching into the design of an IoT edge project. John starts the paper with a quote from Pliny the Elder ...
    by Published on 12-18-2017 06:00 AM
    1. Categories:
    2. Semiconductor IP,
    3. Cadence,
    4. Events,
    5. Artificial Intelligence
    Post Fabless Era - Fabless and Backend Design Less Companies-apple-a11-bionic.jpg

    The consumer Electronics Show is in its 50th year believe it or not! The first one was in New York (1967) with 250 exhibitors and 17,500 attendees. Portable radios and TVs were all the rage followed by VCRs in 1970 and camcorders and compact discs ...
    by Published on 12-17-2017 06:00 AM
    1. Categories:
    2. Semiconductor Manufacturers,
    3. GlobalFoundries,
    4. Intel,
    5. Events,
    6. FinFET
    Article: FinFET Modeling and Extraction at 16-nm-intel-interconnect-stack.jpg

    As I have discussed in previous blogs, IEDM is one of the premier conferences to learn about the latest developments in semiconductor technology.

    by Published on 12-15-2017 11:00 AM
    1. Categories:
    2. Semiconductor IP,
    3. Moortec
    Article: A Brief History of the Fabless Semiconductor Ecosystem-moortec-min.jpg

    In a former life I was the GM of a business where we built specialized structures used for semiconductor process bring-up, characterization and monitoring. These monitoring structures were placed in wafer scribe-lines and were used to monitor key parameters during wafer processing. The structures provided ...
    by Published on 12-15-2017 06:00 AM
    1. Categories:
    2. Semiconductor IP,
    3. RISC-V
    Article: FinFET Modeling and Extraction at 16-nm-1.jpg

    Starting a career in static timing analysis domain, and now actively working on an opensource implementation flow of RISC-V architecture, has been a journey. For last couple of months, I guess from around March this year, I was hooked to RISC-V buzz which was all over my Linkedin, my messages.

    Being an STA and Physical design engineer, it was very ...
    by Published on 12-14-2017 11:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Magwel
    Article: A Comparison of SemiWiki and DeepChip-parasitic-bjt-nmos-min.jpg

    Terms like avalanche breakdown and impact ionization sound like they come from the world of science fiction. They do indeed come from a high stakes world, but one that plays out over and over again here and now, on a microscopic scale in semiconductor devices – namely as part of electrostatic discharge (ESD) protection. Semiconductor devices are highly vulnerable to the high voltage spikes that commonly occur when triboelectric ...
    by Published on 12-14-2017 06:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Synopsys
    Article: A Comparison of SemiWiki and DeepChip-shift-left-verification-min.jpg

    Unless you have been living in a cave for the last several years, by now you know that “Shift Left” is a big priority in product design and delivery, and particularly in verification. Within the semiconductor industry I believe Intel coined this term as early as 2002, though ...
    by Published on 12-13-2017 11:00 AM
    1. Categories:
    2. Synopsys
    What Keeps the executives of Semiconductor awake at night?-complete-set-dsp-features-min.jpg

    Synopsys DesignWare ARC HS4xD family is a perfect example of high performance DSP, enhanced RISC CPU IP core, able to address high-end IoT, mid to high-end audio or baseband control. ARC HS4xD architecture is 10-stage pipeline for high Fmax, resulting in excellent RISC efficiency with 5.2 CoreMark per MHz. ARC EMxD processors are offering lowest ...
    by Published on 12-13-2017 06:00 AM
    1. Categories:
    2. Semiconductor IP,
    3. CEVA,
    4. Events
    Post Fabless Era - Fabless and Backend Design Less Companies-adas-real-time-vision-processing.jpg

    ADAS is in many ways the epicenter of directions in the driverless car (or bus or truck). Short of actually running the car hands-free through a whole trip, ADAS has now advanced beyond mere warnings to providing some level of steering and braking control (in both cases for collision avoidance), providing more adaptive cruise control, adapting ...
    by Published on 12-12-2017 11:00 AM
    1. Categories:
    2. Semiconductor IP,
    3. Synopsys,
    4. Synopsys
    Article: Subsystem IP, myth or reality?-snps-sb-min.jpg

    I recently wrote an article about Synopsys’ DesignWare Security IP for the Internet-of-Things market and was interested to see that a startup, Starblaze Technology, has now used parts of the same IP in its latest Solid-State Drive (SSD) controller. The security IP caught ...

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