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  • HLS update from Mentor about Catapult

    I recall back in the late 1980's when logic synthesis tools were first commercialized, at first they could read in a gate-level netlist from one foundry then output an optimized netlist back into the same foundry. Next, they could migrate your gate-level netlist from Vendor A over to Vendor B, giving design companies some flexibility in negotiating the best foundry terms. Finally, they could accept RTL code as an input, then create foundry-specific gate-level netlists that were optimized.

    Since Synopsys came to dominate the RTL logic synthesis market in the 1990's, many competitors have aimed to sit on top of logic synthesis with their own High Level Synthesis (HLS) tool. EDA vendors have tried over the years with varying degrees of commercial success to grow the HLS market. All of the big three in EDA have made inroads with HLS tools and sub-flows, so I met up with Badru Agarwala, GM at Mentor during DAC in Austin last month to get an update on what's been happening with their Catapult product line.

    Article: Is The Fabless Semiconductor Ecosystem at Risk?-barun-agarwala-min-jpg

    Q: What are the industry trends with HLS these days?

    A: HLS is only one pice of an ecosystem moving up to use the C++ language now, so one goal is to make C++ design as robust as RTL verification is.

    Q: What customers are using HLS, has it gone mainstream yet?

    A: Some big company names that you should recognize that are using HLS now include: NVIDIA, Qualcomm, Google and STMicroelectronics.

    Q: Is there a sweet spot for using an HLS tool flow?

    A: Yes, segments like machine vision, computer vision, 3D TV all enjoy an HLS methodology.

    Q: What about design capacity with HLS, is that an issue?

    A: We've seen a 25 Million gate design completed with Catapult, so the capacity is there.

    Q: What benefits do HLS designers enjoy the most?

    A: Three things that are common benefits include: Verification is more thorough, the design process is much faster than RTL, and designers can make more changes at the last minute of their projects.

    Q: How is HLS impacting the verification process?

    A: Now with HLS you can start verification much earlier than before, in parallel with the design process, then when the code is stable start to do RTL design.

    Article: Is The Fabless Semiconductor Ecosystem at Risk?-catapult-min-jpg
    Q: What are some of the challenges of coding with C++ for an HLS language and how is Catapult changing?

    A: Most existing C++ tools are for SW developers, not really well suited for HW developers, so there's not much linting or property checking going on. HLS users really need coverage tools, along with bit accuracy and loop unrolling. We just announced Catapult DesignChecks to help an HLS user find bugs while coding, so they don't have to debug as much with simulation and synthesis. There's both a static mode of DesignChecks for fast linting plus a formal engine for checking. These approaches don't even require a testbench to be coded.

    A second new tool we're talking about is Catapult Coverage which gives you code coverage for C++ and enables faster closure of synthesized RTL. Designers can reach 100% C coverage, then start to do HLS synthesis. We've had coverage tools for gate-level and RTL, so it only makes sense to raise that up to the C level too.

    We also have SLEC (Sequential Logic Equivalence Checking) HLS a new C to RTL equivalence tool, so that you know that the RTL coming out of Catapult really is the same as the C++ that went into it, without having to run simulation and verification cases. Setup is more automated now.

    Summary
    Mentor with the Catapult family of tools has been at this HLS methodology for a long while now and have continued to invest in making the whole tool flow more integrated and easier to use for digital designs. I was impressed with the three StreamTV engineers in the Mentor booth who showed a 3D TV design using Catapult in their 15 month project because of how few people were required to do such a complex design so quickly, and consumers view 3D without glasses.

    Article: Is The Fabless Semiconductor Ecosystem at Risk?-stream-tv-min-jpg