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  • NetSpeed Bridges the Gap Between Architecture and Implementation

    Article: A Brief History of Aldec-netspeed_unleashing.jpgThis is part II of an article covering NetSpeed’s network-on-chip (NoC) offerings. This article dives a little deeper into what a NoC is and how NetSpeed’s network synthesis tool, NocStudio, helps system architects optimize a NoC for their system-on-a-chip (SoC) design.

    Traditionally IC designers have used proprietary buses, crossbars and switch fabrics to connect their on-chip IPs. These proprietary architectures are fine for simpler ICs but as SoCs become larger and more heterogeneous in nature and foreign IPs are brought in from various sources it has become increasingly difficult to integrate the design using these fabrics. Additionally, dedicated interconnection between multiple IPs requires more wiring, creating congestion and inflating die sizes while possibly leading to increased power consumption to drive the longer interconnects.
    Article: A Brief History of Aldec-wirereduction.jpg
    The alternative is to use a network-on-chip (NoC) that makes use of shared interconnect resources (links and routers) as opposed to dedicated wiring between IPs to reduce the overall wiring required of the inter-IP connections by as much as 30% to 50%. At the simplest level, the NoC is a grid of point-to-point links between the various IP. At the intersections of the grid are specialized on-chip routers that steer data to their destinations. Just as in off-chip networks, data moves from its origin to its destination through a process known as store and forward (SaF) where data is broken into pieces known as packets. Packets contain the data being transferred, called the payload, along with a data header that specifies origin, destination, and a unique ID to establish packet ordering for final re-assembly at the destination. The size of the payload and associated buffers at each network node is determined by the design of the network.

    As packets arrive at a router, they are “stored” in a buffer and a hardware arbiter in the router determines the next downstream location for the packet. The arbiter configures a shared switch and then “forwards” the packet from the buffer to the next node through the switch. Once the packet has moved to the next node the router releases the switch resources so that subsequent packets can use them. Individual packets make their way to their destination in the most efficient way as prescribed by competing traffic on the network. This is repeated until all of the packets reach their destination where they are reassembled in the correct order based on their ordering ID.

    This is admittedly a highly simplified view but you get the gist. There are loads of PhD dissertations on how best to arbitrate channels given different workloads, avoid deadlocking conditions, and make trade-offs for different network configurations depending on the types of data being sent and latency and quality of services (QoS) desired. In short, this is a daunting task for even the most advanced system level designers and can make or break a SoC. The greater the number and variety of cores and modules on the SoC, the more complex the NoC. Data coherency and data security add additional hardware levels on top of this basic physical network level that must also be comprehended.

    Article: A Brief History of Aldec-nocstudio_pyramid.jpgNetSpeed offers multiple value propositions to aid in the process of designing a NoC. These include but are not limited to a seasoned team of professionals that understand network architectures and a set of configurable ready-to-go NoC IP for handling end-to-end QoS requirements within a heterogeneous environment with a mixture of both coherent and non-coherent agents. That in itself is noteworthy, but what got my attention is that they aren’t just supplying IP. NetSpeed has managed to bridge a difficult gap between architecture and implementation.

    NetSpeed’s NocStudio design environment gives the system designer the all-important capability to do “what if” analysis and trade-offs of the various different NoC architectures. It enables the system designer to work at the application level (coherency, QoS, deadlock avoidance), the transport level (different protocol support), the network level (traffic-based optimization, including power analysis), the link level (support for sub-networks, clusters and virtual channels) and the physical level.

    Designers capture IP components and connectivity, define performance requirements and establish high level network requirements between IPs such as bandwidth, latency sensitivity and required QoS. What is different is that where typical system tools stop, NetSpeed keeps going. They took on the challenging task of generating the implementation RTL for all of the logic (routers, arbiters, buffers, coherency controllers, virtual channel logic, pipelining etc.) including taking into account the floorplan, power and performance requirements of the SoC.

    Article: A Brief History of Aldec-nocstudio.jpgThis is not an easy task. There are always trade-offs that must be made to ensure the design is implementable given die size and timing/power budgets. Giving the system designer the ability to iterate based on implementation details is important because it’s at the architectural stage where there is the most leverage to accommodate changes imposed by realities of the implementation.

    NocStudio allows designers to drop all of the desired IP blocks into a floorplan and the tool can then optimize the placement of the IPs and alter the network configuration to meet the various designer specified system requirements. Alternatively, the tool can be given a floorplan and asked to synthesize the best possible network configuration given the floorplan it is given.

    The real trick, however, is being able to automatically generate a correct-by-construction synthesizable RTL implementation of the NoC. Teaching an engineer to write synthesizable RTL code is one thing. Teaching that same engineer what his RTL is supposed to be doing to implement the carefully designed NoC is a whole different and more difficult story. Verifying he implemented what you asked of him is yet another difficult task. NocStudio eliminates the need for this by generating correct-by-construction RTL that implements all of the trade-offs made by the system designer.

    Article: A Brief History of Aldec-3steps.jpgAnd if that weren’t enough the tool also generates a verification test bench and C++ functional models that can be used in the design flow to ensure closure on the final implementation.

    NetSpeed enables not only the design of an incredibly robust NoC, but also the implementation and verification of the same. In my book that’s a pretty complete solution.

    See Also:
    NetSpeed Leverages Machine Learning for Automotive IC End-to-End QoS Solutions
    Automating Front-End SoC Design with NetSpeed’s On-Chip Network IP
    More data at netspeedsystems.com