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  • 3D NAND - Moore's Law in the third dimension

    Article: A Brief History of EDA-3d-nand-samsung-min-jpgFor more than a decade 2D NAND has been the leading driver of lithography shrinks, for example, Samsung went from 120nm in 2003 to 16nm in 2014 with shrinks on an almost yearly basis, but the shrinks came at a price. At 16nm Self Aligned Quadruple Pattering (SAQP) was required for the most critical layers and patterning related costs including deposition and etches for multi-patterning grew to represent nearly two thirds of the cost of the wafer fabrication process. At the same time device related issues were also a growing problem, adjacent cell interference, maintaining control gate to floating gate coupling and the shrinking number of electrons per cell are just a few of the many issues.

    In 2014 Samsung introduced the first 3D NAND part. Instead of horizontal stings of memory cells Samsung turned the strings on end into the vertical direction. The basic process flow can be broken up into three major segments:

    1. CMOS - this is the peripheral circuitry that drives and controls the memory array.
    2. Memory Array - the area where the values are stored.
    3. Interconnect - connects the memory array and CMOS together.

    The CMOS and Interconnect are similar to the 2D NAND process but the memory array formation is completely different. The memory array fabrication is as follows (Samsung TCAT process):

    • Alternating layers of silicon dioxide and silicon nitride are deposited.
    • Channel hole etch - the channel opening is etched down through all of the oxide/nitride layers.
    • Channel fill - an epitaxial layer is grown in the bottom of the channels and then the channel is filled with polysilicon and oxide to create a "macaroni channel" (a tube of polysilicon filled with oxide).
    • Stair Step Formation - a thick photoresist layer is applied and patterned, one set of oxide/nitride pairs is etched and then the photoresist pattern is shrunk and the next pair of oxide/nitride layers is etched. This sequence is repeated to create a stair step structure at the edge of the array. Ideally this is done with a single mask but in practice multiple masks are required.
    • Planarize - a thick oxide layer is now deposited and planarized.
    • WL Slot - a word line slot mask is applied and a slot is etched down through all of the oxide/nitride layer pairs.
    • Gate Formation - the nitride layers are now etched out through the word line slot. A gate stack of silicon dioxide, silicon nitride, aluminum oxide, tungsten and tantalum nitride if then deposited and etched back and finally the slot is filled with oxide and tungsten. This is a gate last process, other companies use a gate first process.

    There are a number of advantages to this process:

    1. The lithography requirements are relaxed because the cell "length" is set by the depositions. All of the memory array patterns are done with single patterning.
    2. The number of cells in a vertical string can be scaled up by depositing more layers. In theory you can add layers without needing any additional masks although the stair step formation may require some additional masks. In theory the whole memory array is fabricated with only three masks although in practice more are required.
    3. The memory cells are bigger and hold more electrons.
    4. Speed, endurance and other critical performance characteristics are all improved versus 2D NAND.

    With 2D NAND we saw memory density improve from 0.006 Gb/mm2 at 120nm to 1.1 Gb/mm2 at 16nm for a 3 bit per cell memory cell. In 2014 Samsung introduce a 24 layer 3D NAND part with 0.97 Gb/mm2 for a 2 bit per cell part, in 2015 Samsung introduced a 32 layer 3 bit/cell part with a density of 1.86 Gb/mm2 and in 2016 a 48 layer 3 bit per cell part with 2.62 Gb/mm2. 3D NAND has already far surpassed the higher memory density of 2D NAND and it is expected that additional layers will continue to be added until parts with over 100 layers and more than 1Tb per part will be introduced. In fact, we forecast that a 128 layer - 4 bit per cell part will be produced around 2020 with 8.67 Gb/mm2.

    3D NAND is not without it challenges, as the number of layers increases it may not be possible to etch and fill through the entire stack and the stack may need to become a two-step process where half the stack is deposited and patterned and then the other half is deposited and patterned. The relatively low mobility of the polysilicon channel may also become limiting and IMEC has already demonstrated InGaAs as a channel material.

    See my article on IMECs work here.

    Another interesting innovation in 3D NAND was disclosed by Intel and Micron at IEDM last year where they fabricate part of the peripheral CMOS under the memory array. The combination of CMOS under the memory array and a denser array enabled Intel-Micron to achieve a 22% density advantage over Samsung for a 32-layer device.

    See my article on the Intel-Micron disclosure here.


    Of course no technology succeeds in the semiconductor industry unless it is economical. The switch to 3D NAND has changed the cost paradigm away from being patterning dominated to being deposition and etch dominated. In fact, I estimate that patterning costs make up less than one third of the total fabrication process for Samsung's 32-layer device (one double patterned layer for interconnect). Some analysts claim that 48 layers is the breakeven technology versus 16nm 2D for bit cost, I disagree with this. 3D versus 2D wafer fabrication costs are similar although with different costs drivers. 3D NAND has much higher bit density but to-date poor yield due to the challenges of pattering the memory stack. My modeling is that Micron's 32-layer part is 25% less expensive per bit than their 16nm 2D NAND after factoring in yield. This is consistent with statements from Micron. Furthermore, Micron has shown a generation 2 part that they say will provide an additional 30% cost reduction over generation 1, also consistent with our modeling.

    In conclusion 3D NAND has overcome the limitations of 2D NAND providing lower cost and better performance with a scaling path into the next decade.