One of the things I really like about major technical conferences is the opportunity to meet with people for networking and interviews. On Wednesday at the Advanced Lithography Conference I had the opportunity to interview Greg Mcinttyre, the director of advanced patterning at IMEC.
IMEC researchers are the first author on 32 to 33 papers at this years SPIE Advanced Lithography Conference with the papers split evenly between EUV, SAQP and DSA.
DSA (directed self-assembly) - IMEC presented 14 papers on DSA. DSA has the highest potential for near term insertion with memory the most interested in DSA implementation. A DSA line/space approach is defectivity limited. A templated via approach can be done with grapho-epitaxy. EUV templates for a templated via can change a double litho-etch (LE) to a single LE. Electrical testing of templated via taken through to electrical test looks as expected with performance tracking hole size. The biggest challenge is defectivity. Memory is expected to use this approach first because it is more defect tolerant. DSA needs to fit into an environment designed for multi-patterning. They are looking at different materials to make DSA fit into today's design environment. The first DSA symposium in Belgium this year. Survey says 2 to 5 years before DSA insertion. Current XSADP going to XSAQP could be replaced with DSA. Some DRAMs have been made with DSA.
EUV - they have a program looking at alternate materials. They have an ASML NXE3300, materials, masks, and pellicles and they are looking at integration. The alternate materials program has multiple partners including inprea, and JSR, and they are looking at metallic concepts, adding metallic sensitizer to chemically amplified photoresist. They are looking at dry develop rinses or adding material that stays in during dry to prevent collapse until you etch it away. They want to understand the latest chemically amplified photoresist capability. As you lower a dose you get more shott noise so they are looking at smoothing in etch tools from TEL and Lam. DSA offers contact hole smoothing on a track.
For pellicles they have an initial solution for 40 to 80 watts full field with 85% single pass transmission. Silicon based pellicles are likely limited to 80 to 100 watts. They are investigating alternate films with carbon nanotube meshes that provide strong mechanical strength and transmission but lack chemical stability in hydrogen. Graphene and silicon nitride films with DSA for holes to improve transmission and mechanical stress in the film are also being looked at. Carbon based films are very promising.
EUV versus 193i integration. EUV imaging is clearly superior and pattern fidelity is there. Throughput, roughness and critical dimension (CDU) are key issues. One EUV layer can replace 3 argon fluoride immersion (ArFi) layers for 32nm IMEC N7.
Metal contamination of scanner, etch and track so far looks OK.
Nigh-NA system, anamorphic was a big breakthrough!
EUV insertion around 2018, if N7 is late 2017 (authors note, this is TSMC's target) then N5 plus N7 cost reduction. The biggest push is from logic. 2D metal is worth a node but then at the next node you are back to 1D. 1D offers better electrical performance and simpler design rules. EUV most likely to be used for single exposure BEOL and as a cut mask for SAQP in the FEOL to replace multiple cut masks.
SAQP (self aligned quadruple patterning) - well controlled 22nm pitch fins with sub nanometer pitch waling. 22nm pitch is ~N5. The big SAQP is process control with CD and roughness varying with height. You need to control every process step, core 1, spacer 1, etc. They are working with ASML and Lam tuning the scanner and the etcher. Just the scanner or etch optimization gets 0.8nm CDU three sigma but co-optimization gets 0.6nm CDU three sigma.
Multi-beam eBeam - they are not focused on eBeam. He thinks multi-beam wafers is a big challenge but multi-beam for masks seems more likley.
Device Technology - Aaron Theon is presenting on the future of new devices. Horizontal nanowires look promising to replace FinFETs. Vertical nanowires versus horizontal nanowires depends on the design with vertical offering better gate length control.