Subi told me his background was in design but that he is now the business unit head for Fab 1 in Dresden. The 22FDX platform is being developed to run in Dresden and will be the next generation process for that fab (Dresden most advanced process is currently a 28nm bulk planar process).
22FDX is targeted at mobile computing and the mobile requirements for cost, performance and power. Applications like the internet of things (IOT) will need ~$1 ASPs. Some of the key requirements include:
- Ultra-low power.
- Security and privacy.
- Always on sensors and modules.
- Dynamic performance and leakage low leakage for always-on and performance for short bursts.
Multi-patterning is driving up wafer costs. A design for a leading edge FinFET process costs $50-$80 million dollars for the design. To get a reasonable return at a 20% market share you are looking at ~$400 million dollars out of a market with a TAM of $2 to $3 billion dollars. Not many opportunities are that large.
FinFETs are used for the highest performance applications but they consume slightly higher power due to 3D capacitance. For everything else planar FDSOI is the best.
The goal with 22FDX was to maximize the shrink from 28nm, while minimizing double patterning. 22FDX can provide FinFET like performance while operating down to 0.4 volts. It is the only technology known today that can operate at that low of a voltage. The technology also offers software tuning of the body bias so that post silicon tuning can be used to dial in performance and recover weak SRAM bits.
My background is in process technology and I was very interested to dig in to how this process is designed. As previously stated GF wanted to minimize multipatterning.
- The front-end-of-line (FEOL) transistor is licensed from ST Micros 14nm FDSOI process.
- Middle-of-line (MOL) includes 2 metal layers (M1 and M2) with double patterning by litho-etch-litho-etch (LE2).
- Back-end-of-line (BEOL) is all single patterned to keep down costs.
The process is basically a 14nm FEOL with a 22nm BEOL to minimize costs.
There are four versions of the process:
- 22FDX-ulp ultra-low power special SRAM and doping optimization.
- 22FDX-uhp ultra-high performance BEOL stack optimization and MIM capacitors.
- 22FDX-ull ultra-low leakage adds dual gate oxide to create a thick oxide ultra-low leakage device.
- 22FDX-rfa RF & analog passive devices and ultra-thick metal.
The 22FDX process offers a wider range of threshold voltage/leakage options than any other known technology. As I will discuss in my forthcoming blog on Greg Yerics plenary talk, options on voltage/leakage are very important to designers.
The use of body biasing in this technology is a key to its performance. Forward biasing the body (FBB) drives up performance and reverse biasing the body (RBB) provides the lowest leakage. FBB and RBB can be done on a block by block basis on a single die. For example, an IOT device might have an always on watchdog processor in a RBB block to minimize power. The rest of the blocks on the chip could be kept off until needed. Additional blocks could include a FBB processor block for high performance and an integrated RF block for off-chip communication. This unique feature of 22FDX allows the integration onto one chip of functions that would typically require separate chips built with different technologies.
22FDX is 50% faster and 18% lower power than a 28nm high-k metal gate (HKMG) technology or 47% lower power at the same frequency. At 0.4 volts an ARM core can run at 520MHz while consuming 92% less power! The RF performance is good enough to implement WiFi or Bluetooth without the need for an external power amplifier.
In terms of the schedule, design kits for 22FDX are available now and risk production is scheduled to begin mid-2016.
Long term FDSOI can scale down to 10nm but they havent decided on the exact node for a follow on process. The 22FDX is kind of an intermediate process between 28nm and 14nm with better performance than 28nm and lower cost than 14nm. Presumably the next version will be positioned between the 14nm and 10nm FinFETs for performance and cost. Subi said the next generation process would likely be in Dresden.
You can view the Global Foundries 22FDX presentation HERE.
Also Read: IEDM Blogs Part 2 Memory Short Course