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  • FDSOI As a Multi-Node Platform

    One of the main criticisms of the FDSOI technology has been that it is a one-node solution at best and is not scalable to the future. Such arguments are typically based on the “gate-length-scaling” assumptions which do not capture the past and current trends of the CMOS technology as I discussed in my earlier post. Back in the early 2000s, the holy grail of the industry was to demonstrate feasibility of MOSFET scaling to a channel length of 10nm or less. Multiple technical papers [1-4] reported bulk planar MOSFETs with gate length going down to sub-10nm regime. With difficulty of scaling bulk transistor already felt and ITRS projections that a 10nm gate length will be needed in 2015, ultra-thin channel structures, such as FinFET and FDSOI [5], were viewed as candidates to scale the gate length to “the end of the roadmap”.

    Article: Network on Chip in Automotive: Arteris-roadmap.jpg

    Figure 1.Global FDSOI landscape.

    With this in mind, rule of thumb recommendations for the required channel thickness were provided based on a combination of early experimental data (with non-aggressive gate stack, junction design, etc.) and TCAD studies. The popular rule of thumb requiring Tsi = Lg/4 for planar FDSOI was based on devices with an oxide thickness of about 2nm [6]. In fact, the authors emphasized that this is somewhat pessimistic assumption and more aggressive scaling should be possible with a high-k/metal gate technology [6]. The advantage of thin BOX FDSOI to further improved the electrostatic control of the device [7] that was reiterated recently as a means to extend FDSOI to 5nm gate length, was also based on the same mindset. While I firmly believe that planar FDSOI technology is salable to 10nm (with the current foundry node naming), to offer a competitive technology is more involved than just a mere gate length scaling (which is by the way not needed). In due course, I will discuss what I envision as a competitive planar 10nm FDSOI technology. Until then you can safely ignore any argument for or against FDSOI scalability.

    Figure 1 is borrowed from the book chapter I wrote with Kangguo Cheng (the man who made high performance FDSOI a reality). At the time of writing the chapter, 28nm was already developed at STMicroelectronics and the agreement to transfer the technology to Samsung was about to be announced. Today, Samsung has announced that 28nm FDSOI is fully qualified for manufacturing, with a record fast yield ramp of about one year. STM has already announced two product chips implemented using 28nm FDSOI; Freescale disclosed that their next i.MX chip will be on the same technology, manufactured by Samsung; and benefits of the technology over 28nm HKMG bulk technology have been discussed by Sony, Cisco, etc.

    Figure 2. Samsung's 28FDSOI timeline

    Technology elements that formed the foundation of the 14nm FDSOI had been also developed by the IBM-ST-Leti alliance team at Albany, NY and transferred to Crolles. These included, among others, the dual in-situ doped RSD process and strained SiGe channel PMOS integration [8] that gave FDSOI a performance unprecedented by any CMOS technology to date. The development of the 14nm FDSOI technology was, however, somewhat slowed down due to the focus of the STM team on 28nm and in part due to lack of proper BEOL tools needed for dual patterning. One could, however, imagine an FDSOI technology with the same performance elements but with a single patterning BEOL. This is in fact what we had used as the test vehicle for the majority of the technology development and is what I marked as a “20nm” FDSOI technology in the chart above. At the time of writing the book chapter, GlobalFoundries was about to kick off the technology development and I am extremely happy that in about one year they have enough confidence to announce a foundry offering at 22nm.

    The above example is what I mean as the “multi-node platform” concept in this article. Being a planar technology, FDSOI allows the FEOL to be independent of the BEOL. In the above example, the same FEOL elements were initially developed with a single pattering BEOL test chip, then transferred to a double-patterning BEOL technology, and finally transferred back to a single-patterning technology, while keeping FEOL almost unchanged throughout this process (with the exception of slight change in gate pitch). This is a very important concept and has been practiced multiple times in the past CMOS technologies whenever a “shrink node” was developed. What was done here, however, is somewhat in the opposite direction; placing a “better MOSFET” at an older node than it was initially intended for, to take advantage of a depreciated foundry process (Fab 1 in Dresden in this example).

    Why Not FinFET?

    One might argue why the same concept cannot be used with FinFET. Assuming that the FinFET cost-adder is only 2-3% (at 22nm) according to Intel, and it delivers 50% or more active power reduction, why none of major foundries offer a FinFET technology with 28nm groundrules? Hey, this would be a much better alternative than various 28nm versions that TSMC is advertising and they might as well market it as a 22nm technology! Cost argument aside, there is a technical problem: FEOL and BEOL are linked together through the choice of fin and metal pitch as I discussed earlier. Taking the case of TSMC’s 16nm technology and assuming that with a 64nm metal pitch the optimum fin pitch is 48nm, at 28nm groundrules the optimum fin pitch would be 60nm or more (This actually coincides with what Intel used in their 22nm node). The consequence? The higher drive current per footprint that is advertised as one of the major benefits of FinFET is gone if you place it at older nodes; unless you make the fins proportionally taller. Manufacturing complexity aside, FEOL capacitance grows in proportion, which defeats any advantage.

    FDSOI at More Mature Nodes

    Throughout my career at IBM, I had been asked a few times by licensing folks if there is any market for an FDSOI technology at more mature nodes, such as 40nm. My answer has been always “of course”. There are many product that do not benefit from the most advanced nodes because they are dominated by analog, passives, or need elements that are not available in leading edge technologies yet, such as embedded non-volatile memory (eNVM). With the coming wave of IoT applications that require such elements and typically need a small die size, there is growing interest in more mature technologies. Recent announcements of older nodes with process tweaked to offer an ultra-low-power (ULP) or ultra-low-leakage (ULL) technology is a testimony to the need for a better transistor even at older nodes. FDSOI’s main propositions, i.e., the record low local transistor mismatch, the ability to compensate for global variation with a body bias, and the ability to reduce threshold voltage, that together allow record low operating voltage, make it the the perfect transistor to lower active power. In the mean time, the ability to modulate the transistor Vt enables a chip to deliver the target performance by lowering Vt and then increase it to suppress leakage when the chip goes into standby.

    At the time of writing the book chapter, LEAP had developed a 65nm FDSOI technology, called silicon on thin BOX (SOTB), and it was qualified at the Renesas fab. Earlier this year, Renesas disclosed their plan to use their 65nm FDSOI technology to reduce power by a factor of 10. While the details of this technology is somewhat different from the 28nm FDSOI technology at ST/Samsung or the 22nm technology at GF, the principle behind low power operation is the same: Use body bias to lower Vt when needed and take advantage of low transistor mismatch to enable low voltage operation, finish the task, and then increase Vt and go to standby. One can imagine a process shrink of this technology to 55nm or 45/40nm to further reduce the die cost. While I cannot disclose any details, it is clear no major foundry affords to ignore #1 MCU company; whether that be Renesas or Freescale+NXP duo.

    Figure 3. Renesas 65nm FDSOI technology offering 10X power reduction

    1. B. Yu, et al., “15 nm gate length planar CMOS transistor,” IEDM, 2001.
    2. F. Boeuf, et al., “16 nm planar NMOSFET manufacturable within state-of-the-art CMOS process thanks to specific design and optimisation,,” IEDM, 2001.
    3. H. Wakabayashi, et al., “Sub-10-nm planar-bulk-CMOS devices using lateral junction control,” IEDM, 2003.
    4. H. Wakabayashi, et al., “Improved sub-10-nm CMOS devices with elevated source/drain extensions by tunneling si-selective-epitaxial-growth,” IEDM, 2005.
    5. B. Doris, et al., “Extreme scaling with ultra-thin Si channel MOSFETs,” IEDM, 2002.
    6. L. Chang, et al., “Extremely scaled silicon nano-CMOS devices,” Proc. IEEE, p. 1860, 2003.
    7. T. Skotnicki, et al., “Innovative materials, devices and CMOS technologies for low-power mobile multimedia,” IEEE Tran. Electron Devices, p. 96, 2008.
    8. A. Khakifirooz, et al., “Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS,” Symp. VLSI Tech., 2012.