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  • SEMICON Day 2: Outlook and Keynote Panel

    The second day of SEMICON West opened with a press conference. Since it was at 7.30 in the morning we all needed the coffee that they provided. For those of us that remember the glory days of DAC some of the statistics were depressing:
    • 45th year (hey, we got them beat on at least one statistic)
    • 692 exhibitors
    • 136 new exhibitors (about the same as DAC total exhibitors this year)
    • 1,220 booths

    The show fills both halves of Moscone and the areas in between and has a colocated solar show that fills Moscone West.

    The press conference always updates the 2015 semiconductor outlook. Currently semiconductor growth estimates from the various people who make them go from 8.0% (Semico Research, Semiconductor Intelligence) down to 3.4%. But everyone is fast bringing them down due to instability in the EU, weakening in the Chinese market, and the weaker yen (that affects forecasts made in dollars). So far this year silicon shipments are, indeed, up 8% year-on-year but that is slowing.

    The SEMI forecast press release is here.

    SEMI forecasts mostly for the equipment industry (SEMI actually is not just the first 4 letters of semiconductor but stands for Semiconductor Equipment and Materials International), although obviously a major input into how much equipment will be purchased is how much acreage of semiconductor will be built.

    The numbers are all over the place. Jan to May this year versus last shows Europe up 17%, Japan up 50% (wow), North America down 22%, Korea up 23%, Taiwan down 26% and China down 20%. The weakness of the Japanese Yen (and the Euro) feed negatively into these numbers. Interesting there is a lot of ramping of 200mm capacity this year and next and, at least anectodally, used 200mm equipment pricing has firmed. SEMI is predicting 3 years of growth (although since of of those years is 2014 I'm not sure it counts as a prediction.

    Who will Apple partner with at 20nm: TSMC, Intel, Both, or Neither?-sc22.jpg

    Then the show opened with a keynote panel about the challenges of getting to sub-14nm. It was moderated by Jo De Boeck of imec, Mike Campbell of Qualcomm, Shubhashish Mitra of Stanford, Calvin Cheung of ASE and Gary Patton. The events guide lists him as being at IBM but he is now the CTO of GlobalFoundries.

    Gary reiterated what I've heard many others say. He is not afraid of the technical challenges of going to the next node, he is sure we will find ways to do that. The challenge is to keep the costs under control. He said he has 10nm and 7nm teams in Malta (New York). Since it is now not possible to get 35-40% cost reduction per transistor anymore there needs to be a focus on how to add more value: RF front-end modules, 3D and 2.5D technologies, and things like Micron's HMC (where IBM made the logic slice).

    Mike of Qualcomm said that it is necessary to take a more system approach and worry about system yield percentage. One challenge is changes due to stress when building 3D designs in tiny packages which affects yield and reliability. He also threw out a statistic that it takes 12-26 weeks to run the verification vectors prior to tapeout.

    Shubhashish said similar things, pointing out that to get things like serious power reduction you have to start from computer architecture, system architecture, packaging. Get it all into a tiny space. It is not just the 7nm or 5nm transistor.

    In fact there was general agreement that debugging issues and reducing variation (in the most general of senses) to reduce them occurring was really important. Especially with time to market constraints. There is no yield model across the while chain. In big systems it can be almost impossible to discover which chip is failing.

    Calvin said that introducing a new packaging product would take 12-18 months and then a 6-month yield ramp. In the old days they would ramp just a few thousand so if they were bad the cost was manageable. Now a Qualcomm chip ramps instantly to millions. A missing piece of the puzzle is that in semiconductor there is a test key in the scribe so many problems can be detected in real time once they are introduced. There needs to be something for assembly since with ramps, millions of parts are lost if something is systematically wrong. With a new node every 12 months this is a huge problem for the OSATs.

    Gary said they use PDF solutions to keep track of systematic yield detractors such as contact that never prints. There is nothing like that for assembly. Even with the front end all the tools speak different languages making it too hard to use data mining.

    Who will Apple partner with at 20nm: TSMC, Intel, Both, or Neither?-sc21.jpgJo finished by asking them their dreams:
    • Shubhashish: 1000X increase in energy efficiency, improved component technologies such as carbon nanobubes
    • Mike: 7nm in volume yielding with the same defects/cm2 as 28nm and the same production ramp. Debug too long
    • Gary wanted a brain. Or components like a brain, low power, resilient, redundant etc
    • I missed what Calvin said. He probably would like the luxury of slower ramps!

    Oh, and at lunch I saw a 22nm FD-SOI wafer at the SOITEC lunch. Only a blank one (it has the insulating box etc all done though), maybe I get to see a real one when I meet GlobalFoundries tomorrow.