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  • SemiWiki at #52DAC: Nominated for Best Paper Award!

    Blogging for Semiwiki is a very good exercise to prepare a paper submission at DAC. Writing a short article using about 600 words to pass one message, and try to deliver this message as clearly as possible. Writing a paper for DAC is very similar, as you have to be synthetic and develop a thesis in 5 slides, no more, as it’s a time limited exercise: 13 minutes to give the complete presentation plus 1 minute for wrap-up. This paper was my very first submission to the Design Automation Conference… but not really the first in semiconductor related conference. I still remember my intense emotion when my first paper was accepted, it was the “3rd Multilevel Interconnect Conference”, already in the Silicon Valley (Santa Clara), but it was in… 1986! By the way, the “MIPI Beyond Mobile” paper was nominated by the Designer Track Technical Program Committee as a DAC Best Paper Candidate!

    systemverilog assertion for a 3x3 unsigned gate-level multiplier-dac-logo.jpg

    I am certainly proud about this nomination, but it could be a good idea to look at the other five nominated papers in competition (listed by order of appearance) …

    systemverilog assertion for a 3x3 unsigned gate-level multiplier-sonics.jpg

    In Low Power IP track: “Taking Advantage of the Dark Silicon Opportunity”, by “Drew Wingards” from Sonics. The Semiwiki readers who are familiar with my blogs have certainly noticed that I frequently put the focus on low power design. Moore’s law is what it is (maybe not dead but certainly facing very strong challenges in term of chip cost and power dissipation) and I think that power efficiency will be mandatory to design future’s chips. In fact to design today’s chip! Using Network-on-Chip (NoC) or Chip Fabric (whatever you name it) to manage not only chip interconnects but also power dissipation in the different blocks looks to be a very good idea. If you want to increase SoC’s power efficiency, you need to partition the SoC in respect with the different functionalities, create specific blocks and manage these from a power perspective… The paper looks attractive; it’s certainly a good candidate!

    systemverilog assertion for a 3x3 unsigned gate-level multiplier-msft_logo_png.jpg

    Still in Low Power IP track: “Techniques for Power and IR Drop Optimization in Sensor Digital IP”, by Aditya Mukherjee from Microsoft Corporation. Even if the sensor market is still a small part of the semiconductor market with $5.7 billion in 2014 (or less than 2% of the total semi market), it’s an essential piece of today’s mobile market and future’s IoT (many) market. It will be interesting to see how Microsoft is dealing with the sensor as a digital IP product…

    systemverilog assertion for a 3x3 unsigned gate-level multiplier-broadcom.svg.jpg

    Before being implemented into a chip an IP stays virtual… No doubt that “IP implementation” is a very important track! Another nominated Best Paper comes from this track: “Effective Analysis and Optimization of On-Chip POP Package Co-Design, for DDR Interfaces”, authored by several people from Broadcom, presented by Chakrapal Kalwa. If you read me you know that I am spending effort on the Interface IP market analysis, and that DDR IP is the largest IP segment. Listening from Broadcom's experience about Package-on-Package (POP) implementation of a DDR interface is certainly a must do!

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    In Subsystem IP & IP integration track, this paper “Design in the Eye of the Hurricane – Building Optimal Vision Subsystem” from Cadence Design Systems, presented by Chris Rowen is the 4th nominated for Best Paper Award. Also a must attend paper! Martin Lund came from Broadcom in 2012 to manage Cadence’s IP business and it took only two years for Martin to make acquisitions (Cosmic Circuit, Evatronix or Tensilica) and boost Cadence’s IP business and position the company as the #2 just behind ARM for processor (and DSP) IP! I would guess that this subsystem is built around a Tensilica processor core… Certainly a good candidate for the Best Paper Award.

    systemverilog assertion for a 3x3 unsigned gate-level multiplier-freescale.jpg

    The last nominated paper comes from the Verification IP track: “Why Testbench Should Control Processor Execution: a Novel Approach to Bridge the Gap Between IP and SoC Verification” presented by Ritesh Agrawal from Freescale Semiconductor. If I understand well, the idea is to use the Verification IP to check for the IP and take the opportunity to verify the complete SoC as well. This is certainly a hot topic as today’s chip design is under the highest ever TTM pressure. The challenge will probably to clearly explain this complex topic in 13 minutes!

    systemverilog assertion for a 3x3 unsigned gate-level multiplier-ipnest.png

    The reader may think that I am afraid of this strong competition, and I must recognize that these entire papers look very attractive as each of these are dealing with a crucial part of the chip design. But, as we say in French “A vaincre sans peril, on triomphe sans gloire” (in “Le Cid” from Corneille in the XVII century). To be honest, I still think that I keep a chance. In fact, I spent more than 6 weeks working full time to analyze the MIPI Ecosystem a couple of months ago before writing this paper, and I have made two presentations at the MIPI Face to Face meeting in Seattle (so I could fine tune the analysis, thanks to the critical review from MIPI technology experts…).

    systemverilog assertion for a 3x3 unsigned gate-level multiplier-ip-vendor-interface-type-2012-2015.jpg

    I have created a specific tool to analyze this ecosystem in 2015, compare it with 2012 (see this example of MIPI specification support by IP vendors evolution between 2012 and 2015 on the above picture) and scientifically derive trends about MIPI technology pervasion in emerging systems like wearable or IoT in the future. Such analysis aiming to be used by IP vendors to focus on the MIPI interface specifications which will be effectively used “beyond mobile” in the future!

    From Eric Esteve from IPNEST