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  • EUV Makes Progress and Other Observations From SPIE

    The SPIE Advanced Lithography Conference is the world’s premier conference for patterning techniques utilized to manufacture semiconductors. At any given time during the conference there are multiple parallel sessions so it is impossible to see all of the papers presented. Prior to the conference I reviewed and blogged on some of the papers I was most interested in seeing presented. Now as the conference unfolds I wanted to blog about a few papers from each day that I thought were particularly interesting.

    Monday 2/23 – day 1

    EUV for SOC: Does it really help - Greg Yaric, ARM

    The first thing that really struck me about this talk was the disconnect between transistor scaling and what actually happens in designs. My background is in processing and as process engineers we like to track scaling using metrics like gate pitch multiplied by metal pitch and SRAM cell size (and in fact he referenced both). By both of these metrics we are continuing to see scaling along historical trends. However, what was pointed out in this talk is that SRAM cell sizes reported in the literature are for 6T SRAM cells, in critical applications 8T and 10T SRAM cells are becoming common so even though transistors are scaling it doesn’t necessarily translate to designs. Even when a 6T SRAM cell is used it often has 2 fins per transistor. This has resulted in a situation where if you compare SRAM cell size versus frequency for 28nm to 14nm you see a 4X improvement in size at low frequency but at high frequency the size advantage gets much smaller. Many other issues all add together to create a situation where there can be cases where a longer gate length can actually result in a smaller die due to the ability to drive longer wires, avoid repeaters and other factors.

    It was also discussed how gate length scaling has been slowing due to electrostatics and the increasing problems that variability creates. We got a one-time improvement with the move to FinFETs where the lower channel doping improves variability. It was expressed that FinFETs are great at 14nm and OK at 10nm but may not make 7nm without further improvements. Possible increased channel mobility materials like germanium look good in theory but in practice realistic contact resistance and contact size negates many of the advantages.

    Via resistance is also a significant issue. If you look at Intel’s 14nm process the via aspect ratios have been reduced for that reason.

    A hidden problem in the last few nodes is a half node to one node loss in scaling at metal due to all the new layout rules. Metal 1 rules are now so complex that routers can’t handle them and there has been an approximately 20% loss in area. This is where EUV could make a big impact, by relaxing the design rules the half to full node loss could be recovered. In the front end of the line (FEOL) SADP has resulted in improved LER and it was suggested that it was unlikely we would move back to single exposure but in the back end of line (BEOL) EUV could have a big impact.

    To summarize this talk I would say there are a lot more challenges to scaling than just lithography. EUV has the potential to help but mostly in the BEOL.

    Status of EUV Lithography – Anthony Ten, TSMC
    Last year TSMC gave a very pessimistic assessment of EUV, this year the news was much better.

    Last year at this time TSMC was only seeing about 10 watts of source power at intermediate focus, this year it is up to 90 watts. This represents the first time EUV has actually hit a source power milestone, in fact it is slightly ahead of where they thought they would be. The forward forecast is for 125 watts late Q2 and 250 watts late Q4. Both of these forecast goals will require the second generation light source.

    Average tool availability is still only running 55%. Over an 8 week period with a 40 watt source TSMC ran 203 wafers/day for a total of 11,375 wafers (current ArFi tools can run >200 wafers per hour). After the 80 watt upgrade TSMC ran 1,022 wafers in a single day. These numbers are a huge improvement from last year although they still need to double for production. The tin droplet generator has to be replaced approximately every 4 days and it takes most of a day. ASML is working on an improved droplet generator. The droplet generator has to run at an amazing 50,000 droplets per second!

    Current EUV photoresist are good down to a 16nm half-pitch, below that the required dose rises rapidly. A new photoresist with less blur is needed and there is a lot of work being done on metal based photoresists.

    Mask blank defects are getting better but are still too high. With low enough defects and a precise map the defects can be hidden under an absorber. Current blanks can be used for via and contact but not for line/space masks. Mask inspection and repair is also still a work in progress. The following table summarizes the status:

    Inspection typeCurrentIntermediateFinal solution
    Mask blank193nm13.5nm (actinic)
    Patterned mask193nmeBeam13.5nm (actinic)
    Defect repairWafer printing13.5nm (actinic) tool from Zeis due later this year

    Pellicle development has produced a half size pellicle with 85.5% transmission. A full size pellicle with >90% transmission is still needed. TSMC is targeting a full size pellicle by the end of Q2.

    In summary, excellent progress has been made this year but there is still a lot of work to be done before EUV is ready for high volume manufacturing. Assuming everything stays on track we could see readiness in 2016, possibly for a late 10nm node insertion. The question will then become how does EUV match up versus multi patterning solutions on a layer by layer basis.