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  • Who Will Lead at 10nm?

    There has been a lot of discussion on SemiWiki lately around 14nm FinFET technology and who really leads and by how much. I thought it would be interesting to review some process metrics for previous technology generation and then make some forecasts around 10nm.

    The focus of this article will be Intel, TSMC and Global Foundries/Samsung as the logic volume leaders:
    • Intel is the world’s largest semiconductor and far and away the largest IDM logic producer today.
    • TSMC is the world’s largest foundry
    • Global Foundries is the world’s second largest foundry. We have combined them with Samsung because they are both members of the common platform alliance and closely aligned in process technology. In fact Global Foundries has licensed Samsung’s 14nm FinFET process technology.

    The characterization of process density has shifted over the years and nodes have become less reflective of actual feature sizes and density. A more recent metric that Intel has been using is Gate Pitch (GP) multiplied by Metal 1 Pitch (M1P). This same metric has also shown up in a recent paper by the common platform partners disclosing their 10nm process work. GP x M1P will be the metric used for comparison in this paper.

    Intel
    The following table presents Intel’s GP, GP shrink ratio, M1P, M1P shrink ration and GP x M1P starting at 130nm and projecting out to 10nm.

    130nm90nm65nm45nm32nm22nm14nm10nm
    GP319260220180112.5907055
    GP shrink0.820.850.820.630.800.780.78
    M1P350220210160112.5905238
    M1P shrink0.630.950.760.700.800.580.74
    GP x M1P111,65057,20046,20028,80012,6568,1003,6402,101
    All of the pitches down through 14nm are based on Intel public disclosures at IEDM and the IDF. The 10nm forecast is based on applying the average shrink ratio from the previous seven process generations.

    TSMC

    The following table presents TSMC’s GP, GP shrink ratio, M1P, M1P shrink ration and GP x M1P starting at 130nm and projecting out to 10nm.

    130nm90nm65nm40nm28nm20nm16nm10nm
    GP310240160162122879070
    GP shrink0.770.671.010.750.711.030.78
    M1P34024018012895676446
    M1P shrink0.710.750.710.740.701.000.72
    GP x M1P105,40057,60028,80020,73611,5905,8295,7603,220
    In the case of TSMC they follow the “Foundry” node progress whereas Intel follows more of an “IDM” node transition 40nm versus 45nm, 28nnm versus 32nm and 20nm versus 22nm. At the 14nm node TSMC has also chosen to call their node 16nm where everyone else is calling it 14nm.

    We have updated this article with actual measured 28nm and 20nm pitch numbers from Chipworks. At 16nm the pitches are based on TSMC’s 2013 IEDM paper. TSMC’s 16nm is reported to have the same metal pitches as their 20nm so we have used the same pitch for 20nm M1. The 16nm gate pitch is larger than our projected gate pitch for 20nm, this is due to the planar to FinFET transition. The 10nm pitches are based on the average TSMC shrink ratios through 20nm. We have excluded 16nm due to the metal pitch pause and planar to FinFET transition.

    Global Foundries/Samsung (GF/S)

    The following table presents GF/S’s GP, GP shrink ratio, M1P, M1P shrink ration and GP x M1P starting at 130nm and projecting out to 10nm.

    130nm90nm65nm40nm28nm20nm14nm10nm
    GP35024520012990647864
    GP shrink0.700.820.650.700.711.220.82
    M1P35024518011796646448
    M1P shrink0.700.730.650.820.671.000.75
    GP x M1P122,50060,02536,00015,0938,6404,0904,9923,072
    We do not have actual pitch numbers for GF/S 20nm technology and we have interpolated them based on available data. At 14nm and 10nm the pitches are based on published values including the 2014 VLSIT 10nm paper from IBM, Samsung, St Micro and Global Foundries.

    Density Comparisons
    Having reviewed the three companies/groups we can now compare the GP x M1P metric over the range of nodes studied.

    130nm90nm65nm45/40nm32/28nm22/20nm16/14nm10nm
    Intel111,65057,20046,20038,80012,6568,1003,6402,101
    TSMC105,40057,60028,80020,73611,5905,8295,7603,220
    GF/S122,50060,02536,00015,0938,6404,0904,9923,072
    This table has been updated since the original post based on measured TSMC 28nm and 20nm pitches from Chipworks. In the table above I have marked in bold the densest process at each node. It is interesting to see that it has moved around from node to node. Based on what has been disclosed to date and reasonable projections it looks like Intel will have the densest process at 16/14nm and 10nm using the GP x M1P metric. Whether this translates into a denser process for actual designs is a different question but GP x M1P is in our opinion a good measure of pure process density.

    The same data is also plotted below as the now infamous Intel density comparison:

    Article: AMD and GlobalFoundries?-10nm-graph.jpg