In this market it seems to be driven by the 64-bit ARMv8 instruction set architecture. Since servers and networking had already gone to 64-bit, they didn't want to go back to 32 bit and so couldn't switch to ARM until recently.
Most embedded vendors have announced ARM plans:
- AppliedMicro (powerPC) is sampling X-gene
- Cavium developing ARM-based Thunder to complement their MIPS-based Octeon
- Freescale (powerPC) announced an ARM-based communication at the conference
- LSI (powerPC) is sampling an ARM-based version of Axxia
- AMD (x86) developing Hierofalcon for embedded market
- Broadcom announced a new CPU architecture based on ARMv8
Linley's view is that he doesn't think the dual architecture (ARM + another) will endure since it is too expensive to validate CPU and software for two ISAs. I'm not so sure since the cost of doing this seems to be decreasing. For example, David Hass of Broadcom said that their software stack is generally portable across instruction sets (MIPS, ARM and x86, all of which they use). There is a standard programming model, toolchain, APIs, networking specific libraries and so on. It allows network applications to run on any architecture.
Also, having two ISAs gives them a lot of negotiating flexibility and keeps everyone, including ARM, technically on their toes so that if any vendor falls behind it isn't a big problem. MIPS-based systems had this problem a couple of years (ok, more like 10) ago when MIPS wasn't able to invest enough to produce actual cores and the whole future of the company was uncertain. If people already had a dual-ISA strategy it would have been easier to migrate away.
It takes years for these architectural changes to work through the entire supply chain. PowerPC still dominates the architecture share today, witha share of close to 50%. x86 and MIPS are around a quarter each with ARM a trivial sliver. But, as Linley pointed out, this pie charge will look very different in a few years time.
Many IP vendors are also targeting the communications market:
- ARM is becoming the standard for software development
- MIPS competes for high-end networking (new announcement earlier in the week)
- Xtensa (Tensilica/Cadence) offers instruction-set customization (and a new announcement at the conference)
- Andes has small low-power CPUs for embedded applications (and a new announcement at the conference)
- CEVA is the leading vendor of DSP cores (and a new announcement at the conference)
- ASOCS optimizes its DSP cores for wireless base stations (and a new announcement at the conference)
And it is not just CPUs. SoC interconnect can be a bottleneck. A high-bandwidth network on chip (NoC) is required:
- ARM now complements its CPU with CoreLink (and new announcements at the conference)
- Netspeed uses directory-based coherence
- Arteris offer NoC interconnect, as does Sonics