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    by Published on 02-19-2014 06:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Sage DA
    content/attachments/10187-pic1.1.jpg

    DRVerify is part of the iDRM design rule compiler platform from Sage DA, something that I have been personally involved with for the past three years. DRVerify is mainly used to verify third party design rule check (DRC) decks and ensure that they correctly, completely and accurately represent the design rule specification. In addition, DRVerify can be used to clarify and validate the exact meaning of a complex design rule description, as well as to ensure design rule consistency and prevent potential conflicts between different rules.

    Using ...
    by Published on 02-05-2014 06:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Sage DA
    content/attachments/10042-sage-da-1.png

    iDRM (integrated design rule manager) from Sage-DA is the world's first and only design rule compiler. As such it is used to develop and capture design rules graphically, and can be used by non-programmers to quickly capture very complex and shape dependent design rules and immediately generate a check for them. The tool can also be used for layout profiling: it detects every instance of a design rule or pattern, ...
    by Published on 05-26-2013 05:55 AM
    1. Categories:
    2. Semiconductor Design,
    3. Sage DA
    content/attachments/7390-wpe-pattern.jpg

    In advanced process technologies, electrical and timing problems due to variability can become a big issue. Due to various processing effects, a circuit performance (both speed and power) is dependent on specific layout attributes and can vary a lot from instance to instance. The accumulated effects can be severe to the point that it may cause the circuit to fail.

    In this blog I will demonstrate how iDRM is used very effectively to measure and analyze millions or even billions of layout instances and determine possible impact on performance. We will focus on two layout dependent ...
    by Published on 05-11-2013 06:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Sage DA
    content/attachments/7187-file1-rule.jpg

    Much awaited, automatic tool for DRM (Design Rule Manual) and DRC (Design Rule Check) deck creation is here now! I am particularly excited to know about this because I had been hearing for its need (in different context) from the designers with whom I was working to improve their design productivity through the use of our EDA tools (in my past company). Considering ever growing size and complexity of DRM (in terms ...
    by Published on 05-07-2013 05:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Sage DA
    content/attachments/7081-idrm-concept.jpg

    This is an example of what I do during the day. I work with emerging companies on disruptive technologies and help launch them into the fabless semiconductor ecosystem. This product, iDRM, is the result of three years of joint development work amongst three semiconductor foundries and some of their top customers:

    ...