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    by Published on 05-20-2013 05:00 AM
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    Today Cadence announced Tempus, their new timing signoff solution. This has been in development for at least a couple of years and has been built from the ground up to be massively parallelized. Not just that different corners can be run in parallel (which is basically straightforward) but that large designs can be partitioned across multiple servers too. So Tempus is ...
    by Published on 05-19-2013 07:30 PM
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    It goes without saying that registers play a vital role in designing any ASIC, FPGA, SoC or System. In today’s world, while designing SoC with multiple IPs and functionalities on the same chip, registers stay at the heart of the design right from the architectural level as they are used for key interfaces between hardware, software, firmware and even IPs. Register buses ...
    by Published on 05-19-2013 07:01 PM
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    Funny story, @ #49DAC I saw Aart with a very relaxed look on his face looking at the exhibit hall and in my mind he was thinking, "Mine, all mine!" But I digress....... Synopsys is the #1 EDA company for a reason and here is the supporting data for that hypothesis:

    Synopsys is committed to accelerating Innovation for its customers—it’s been at the core of the company’s DNA for more than 25 years. The world’s leading semiconductor and electronics ...
    by Published on 05-19-2013 06:30 PM
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    In a complex semiconductor market today, characterized by ever increasing design size and complexity, long design cycle, rapid technological advancement, intense competition, pricing pressure, small window of opportunity, development and cross-functional teams spread across the globe and multiple design partners including several IP vendors for a single SoC, it’s essential for a corporate to identify key strategies for its sustainable competitive advantage. Among ...
    by Published on 05-19-2013 06:10 PM
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    Invarian is an interesting EDA company that sees a niche market opening in the physical verification space. There are a number of converging factors that are driving this opportunity. It seems like everything is going 3D these days, from FinFETs to heterogeneous stacked-die packaging. In a 3D world thermal effects have a major impact on power, performance and reliability. Electromigration ...
    by Published on 05-19-2013 05:45 PM
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    Last week Berkeley Design Automation introduced a new Analog Characterization Environment (ACE) – a high-productivity system to ensure analog circuits meet all specifications under all expected operational, environmental, and process conditions prior to tapeout.

    While standard cell characterization and memory characterization are well defined application areas with standard flows, dedicated tooling, and rigorous metrics to ensure high quality results, analog ...
    by Published on 05-19-2013 03:58 PM
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    Today Oasys announced the availability of Floorplan Compler in the Oasys RealTime suite of physical RTL exploration and synthesis tools. This is actually a repackaging of a capability that has always been in RealTime Designer, and in fact has been an important aspect of how well RealTime Designer has performed in benchmarks over the last four years. ...
    by Published on 05-19-2013 01:25 PM
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    Dassault Systèmes is not a company entirely new to DAC, but with the acquisition of Matrix One (which had already acquired DesignSync) a few years ago and Tuscany Design Automation's PinPoint last year they now have a richer portfolio to support various aspects of electronic design. By the way, Dassault is a French company so if you want to be correct you should pronounce it the French way, ...
    by Published on 05-19-2013 08:40 AM
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    EDA software is quite different from off-the-shelf software. In most cases, customer requirements are unique and depend on the proprietary and complex design process, environments and standards developed and/or evolved by semiconductor design teams over a number of years. EDA software ends up being heavily customized to conform to the customer’s standards and design flow. ...
    by Published on 05-18-2013 10:00 PM
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    I recently had the opportunity to interview Jason Xing, Ph.D., CEO and President of ICScape, Inc. Below is a subset of the nearly two hour long interview.

    How did you first become involved in EDA?
    My EDA career started in the mid-90s when I started working on my PhD thesis at the University of Illinois in Urbana-Champaign. My thesis topic was on parallel algorithms for standard cell based placement. After ...

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