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    Published on 04-24-2014 09:00 AM
    1. Categories:
    2. Semiconductor IP,
    3. Mobiveil

    A number of technical and business trends are converging to create a booming market for solid state drives (SSDs), with gigabytes of flash memory capacity along with the related control electronics packaged in the form factor of a 1.8”‐, 2.5”‐ or 3.5”. storage device. The first is the emergence of tablets and pervasiveness of smart phones both of which use flash as their main storage. ...
    by Published on 04-23-2014 08:53 AM
    1. Categories:
    2. Semiconductor IP,
    3. ARM

    ARM announced their Q1 results yesterday. Having just written that Intel lost $1B in mobile, I guess I could have used the title "ARM didn't lose $1B in mobile." They made $100M (on revenues of $300M). So let's start off with what their results actually were and then look at what other things of interest they said on the conference call.

    Q1 net profit rose to $104.7M
    Revenue climbed 10% to $305.2M
    Processor licensing revenue +38% in dollar terms; ...
    by Published on 04-23-2014 01:46 AM
    1. Categories:
    2. Semiconductor IP,
    3. Synopsys

    Thanks to memory controller expert Marc Greenberg, Marketing Director for DDRn Controller IP with Synopsys, for this post “Qualcomm announces first application processor with LPDDR4 capability”. According with Marc, this Application Processor, the Snapdragon 810, is “the first product that I’m aware of that will use LPDDR4 memory”. In fact, the Snapdragon 810 will be sampling by the second ...
    by Published on 04-22-2014 11:52 PM
    1. Categories:
    2. Semiconductor Design,
    3. Aldec

    Learning an HDL language or an HDL simulator are two different things, so I wanted to see what was available for learning a vendor-specific HDL simulator. I've already taught Verilog as an instructor using both ModelSim and Active-HDL simulators, however we only used a handful of commands in the class and labs in order to focus on the language. I found out that an engineer at Aldec created a three part webinar on learning their HDL simulator, Active-HDL, so I watched part one, a 65 minutes video. The basic idea was to cover several key simulator concepts:

    by Published on 04-22-2014 07:51 PM
    1. Categories:
    2. Semiconductor Services,
    3. eSilicon

    Pop quiz: eSilicon has a big IP development group in what Asian country? If you didn't know and you guessed, you probably got it wrong with China or India. It is Vietnam. In fact they have two sites. One in Ho Chi Minh City (that used to be called Saigon) and one in Da Nang.

    At Electronic Design Process Symposium (EDPS) held last week Patrick Soheill who is VP of the IP BU gave the eSilicon ...
    by Published on 04-22-2014 06:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Aldec

    “Failure to plan is planning to fail.” If that is true – and it has been quoted verbatim or slightly modified so many times throughout modern history, there has to be some truth – why does most of the engineering community seem to detest planning so much?

    Engineering planning doesn’t mean whipping out a block diagram or pseudo code, then off to the implementation races – that worked in the old embedded days, and may still work in Makerville, with relatively small projects and few interfacing requirements. For bigger, sometimes safety-critical projects and the system-of-systems with ...
    by Published on 04-22-2014 06:00 AM
    1. Categories:
    2. Semiconductor IP,
    3. Sonics

    We have had the Snowden revelations that the NSA has gone rogue, Target lost a zillion credit cards, the Heartbleed bug meaning that main security protocol of the internet had been coded up wrong for a couple of years, theft of records from RSA and more. One result is that people do not completely trust a security system that depends only on software. It is too easy to break into it. People want to see that low levels of ...
    by Published on 04-22-2014 04:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Cliosoft

    In an era of SoCs with millions of gates, hundreds of IPs and multiple ways to verify designs through several stages of transformations at different levels of hierarchies, it is increasingly difficult to handle such large data in a consistent and efficient way. The hardware and software, and their interactions, have to be consistent through appropriate files and interfaces. ...
    by Published on 04-21-2014 06:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Concept Engineering

    In a complex world of SoCs with multi-million gates and IPs from several heterogeneous sources, verification of a complete semiconductor design has become extremely difficult, and it’s not enough. In order to ascertain the right intent of the design throughout the design cycle, debugging at various stages of the design cycle has to go hand-in-hand along with the design and verification; the architect of the design should be able to make expert judgement and take appropriate action before a small weakness in the design ...
    by Published on 04-21-2014 02:06 PM
    1. Categories:
    2. Semiconductor Design,
    3. Cadence,
    4. Jasper DA

    Cadence announced today that it is acquiring Jasper Design Automation for $170M in an all-cash offer. Jasper has $24M in cash so it is really an acquisition for around $145M. i think that is around 4X revenue but I only know rumors about Jasper's revenue numbers.

    All the big 3 already have their own formal technology but the technology ...

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