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  • Synopsys IC Validator at DAC

    At DAC last week I visited the Synopsys demo suite to see what's new with IC Validator.

    iPDK is the way to go for AMS Designs-icvalidator_ds-fig1.jpg

    Stelios Diamantidis, PMM
    - In-design physical verification
    - Sign-off reveals thousands of late stage DRC violations
    - 28nm has 1.5K rules, 15K runset sizes
    - Metal Fill changes timing
    - The DRM can be changed throughout the life of the process

    Timing Closure – can be too slow, too many iterations, too time consuming
    - A new methodology is needed

    IC Validator – verify as you go, early, not at the end of routing
    - Run during: Floorplan, P/G, Placement, CTS, final route

    In-Design PV: Metal Fill
    - Foundry runset used by IC Compiler
    - Evaluate timing of critical nets, timing aware metal fill
    - Automate ECO process, identify shorts, push route out, comply to DRC rules
    - Example of timing driven metal fill evaluation
    o Renesas: 6X faster TAT using ICV with ICC
    o AMD: 30 minutes to complete Metal Fill, 580K nets

    In-Design PV: Signoff DRC
    - Incremental Checking (analysis by Layer, Area or rule)
    - GDS Merge – remove cell boundaries (full mask checking on demand)
    - Automatic DRC Repair (highly localized, router driven), router told where to correct violations
    - ST: Used the flow to find and fix 340 violations in just 35 minutes
    - TI: Up to 100% auto fix rate , Automatic DRC Repair (ADR)

    Smart Error Management
    - Milkyway Intgration (direct access to properties)
    - Error categorization (automatic linking of violations)
    - Interactive filtering (querying or sorting of violations)

    Chris Grossman – Corporate AE
    Demo of IC Validator, live
    - Start with IC Compiler, DRC checking shows 20,330 violations
    - Stepping through each DRC violation graphically, decide how to fix DRV violations with scripting or manual efforts
    - Another way is to use ICV (DRC checking) inside of ICC (P&R)
    - Results of DRC checking shows only 3926 violations, not 20,330 at the end of detailed P&R
    o Filter the DRC violations: P/G Nets, Clock Nets, Signal Routes, User Routes
    o Re-run just one rule at a time, re-run rules in one rectangular area at a time
    o You can leave the floorplanning stage knowing that you are DRC clean
    o After checking DRC after PG, it’s time to run DRC after Clock Tree Synthesis (CTS)
    o Now only 16 DRC violations found (Found a RAM placement too close to a VDD)
    o Run MergeGDS to see where this RAM instance has a DRC violation
    o After CTS time to run detailed routing, found only 143 DRC violations now

    - Run In-Design PV at each stage of physical design, not at the end of detailed routing
    - In-design physical verification saves weeks of time over the old implement then verify approach
    - IC Validator: pre-routing checks, routing checking, automatic repair, timing aware repair
    o Next release: 1.5X faster DRC runs, 1.5X smaller fill size, 3X less fill memory
    o 20nm: double patterning required, native DPT coloring engine, In-Design decomposition checking
    o Equation-based DRC
    o Debug Productivity: will have a new LVS graphical schematic viewer, LVS equivalent error browser, graphical runset debugger
    o Advanced Nodes: fill-to-target (correct by construction), pattern matching (Prevents manufacturing limiting layout patterns)

    ICC - Has 60% market share in P&R

    This article was originally published in forum thread: Best #48DAC Trip Report Gets an iPAD2 started by admin View original post