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  • Intel 2014 Investor Meeting and 14nm Status

    Intelís investor meeting was held yesterday and for me the presentation that is most interesting is Bill Holtís. The presentations are available on the Intel website: Intel Corporation - Presentations Material 2014. Here is the 2013 version of this presentation: Intel Corporation - Presentations Materials 2013. First off I want to vent a little, what is up with the European paper size? Does Intel have a secret plan to get everyone in the US to buy new printers?

    On slides 3, 4 and 5, the 14nm yields are shown versus 22nm. The good news for Intel is the yields are finally looking pretty good; the bad news is it has taken a long time to get there. I find it interesting that TSMC is reportedly already getting good yields on their 16nm process suggesting their 16nm/14nm development has proceeded more smoothly than Intelís. From what I have heard Samsung and Global Foundries continue to struggle with 14nm yields.

    On slide 7, 14nm pitches of 42nm for STI, 70nm for gate (GP) and 52nm for M1 (M1P) are presented. This is in contrast to TSMCís pitches of 48nm for STI, 90nm for GP and 64nm for M1P as reported at IEDM 2013. This gives a GP x M1P of 3,640nm2 for Intel and 5,760nm2 for TSMC. I have two observations on this:

    1. This is comparing Intelís 14nm to TSMC 16FF. At the 2014 IEDM on December 15, 2014 TSMC is scheduled to present what looks to be 16FF+. It will be interesting to see what if any pitch improvements they report for 16FF+ versus 16FF and how that compares to Intel. The TSMC 16FF GP and M1P are the same as 20SOC, at the 2014 TSMC technology symposium 16FF+ was reported to offer a 15% improvement over 20SOC so perhaps GP x M1P is something like 4,896. I should note here that I have had someone who should know what they are talking about tells me the 16FF+ does not improve density versus 16FF.
    2. The BEOL pitches for Intelís 14nm process have started to come out. My understanding is there are 8 layers of 52nm pitch metal produced with Self Aligned Double Patterning (SADP) followed by 80nm and 160nm pitch layers with air gaps and finally 3 layers of presumably large pitch metal. The use of SADP for the first 8 metal layers means they are 1D metal layers and the design rules are very restrictive. It seems unlikely to me that a foundry could get away with such restrictive rules and this is a key part of why Intel can produce smaller metal pitches than anyone else (more on the metal layers later).

    Slide 8 shows a 0.54x scaling in SRAM size, an impressive achievement!

    Slides 9 through 14 present fin scaling and show scaling to a smaller pitch while simultaneously increasing the fin height. This is another impressive achievement.

    Slide 15 presents Intelís leadership in introducing new process technologies to the industry. Once again these achievements are impressive and it illustrates how much Intel has helped to drive the industry forward over the last decade. The key question this slide doesnít address is what is next and will Intel maintain a lead. TSMC, Samsung and Global Foundries are all ramping up their FinFET processes and have essentially ďcaught upĒ on that innovation. In my opinion the next innovation will be Germanium or Indium Gallium Arsenide fins and it will be interesting to see who get there first.

    Slides 18 and 19 present the 14nm Interconnect. I have to say I am very surprised by the 13 layers of interconnect at 14nm (the number of metal layers isnít listed here and is from other sources). Intel had 6 metal layers for 180nm and 130nm while transitioning from aluminum to copper metallization; at 90nm they had 7 metal layers, 8 metal layers at 65nm and then 9 metal layers at 45nm, 32nm and 22nm. My expectation at 14nm was 10 metal layers. What I think happened was the use of SADP to produce the 52nm critical metal pitches forced 1D metal and a lot of metal layers to accomplish the required interconnect. My ďguessí is:

    • M1 through M8 are alternating x and y direction metal layers all serving for short signal runs.
    • M9 and M10 reportedly have air gaps and presumably these are longer signal runs where the air gaps are need to lower the RC delay.
    • M11, M12 and M13 are presumably large pitch metal runs for power and ground.

    Slide 20 is a new version of the ďinfamousĒ slide showing Intelís density lead. In the past the x-axis has been node but has now been switched to time. Now instead of Intel lagging and then pulling ahead they consistently lead. The following is my own version of this slide comparing Intel and TSMC actual processes and then forecasting TSMC 16FF+ with a 15% shrink and 10nm with a 2.2 density improvement based on the TSMC technology symposium early guidance (these are updated projection since my ďWho will lead at 10nm postĒ). For Intel I used my own trend projected 10nm numbers.
    VIP : Changing landscape - Part 2-intel-vs-tsmc-graph.jpg

    Intel Versus TSMC GP x M1P by year of technology introduction.

    As can be seen from this plot, Intel consistently leads for density; the problem to me with this analysis is until recently Intel was exclusively using their processes for microprocessors (MPU) which have a much narrower set of performance requirements than processes for foundry use. Intel only had to focus on fast transistors while TSMC has to provide processes that meet a wide variety of different requirements. At 22nm Intelís MPU and foundry processes have the same pitches for GP and M1P but will that hold at 14nm and if so how many customers will accept the restrictive design rules required for SADP metal layers?

    Slides 22 and 23 show Mooreís law is alive and well at least at Intel. The cost per wafer goes up with each generation but the die shrinks more than make up for it. As we have entered the multi-patterning era wafer costs are rising faster than we have historically seen but at least at Intel the die shrinks are overcoming this.

    Some observers believe that at the foundries the increase in wafer cost at 20nm due to multi-patterning has overwhelmed the die shrink and die costs have risen. I do not believe this but rather think the die cost reductions have slowed. At the 16nm/14nm node at foundries the wafer costs will again increase (although the use of 20nm backend pitches mitigates this to some extent) and the shrinks are minimal. At 16nm/14nm die cost reductions will be minimal at best. At 10nm I expect foundries to deliver competitive cost per die reductions as we get back to full shrinks, in fact TSMC has guided a 2.2x increase in density. Wafer costs from 16nm to 10nm at TSMC are not going to go up anywhere near 2.2x!

    All in all Intel continues to deliver impressive technological progress and do it economically. Comparing Intel with TSMC (or any foundry) for device area is really not a valid comparison until Intel is a substantial foundry player and the processes being compared are both being used in the foundry space.

    I am still going through all of the presentations but I also wanted to comment on Stacy Smithís presentation slide 51 which shows Intelís fab capacity and demand coming back into balance, which is a really big deal after the low levels of loading seen in 2012 and 2013.