Sometime in Jun/July this year, it was reported by TSMC that their risk production of 20nm chips has already started and volume production will start by Dec this year or early next year. It is known that Apple (for its A8 processors), its first customer is already lined up, more may join the queue. It must be noted that in last quarter of 2012 TSMC also announced support of double patterning technology and multi-die integration and corresponding reference flows for 20nm process node.
For proliferation of this technology into mass production by leveraging the sea of design houses, EDA vendors must provide the complete holistic solutions to overcome these challenges rather than point tools. At 20nm, that need becomes more prominent because it changes the paradigm in the context of double patterning complexities, variability and interdependence between design phases and manufacturing. The designers can no longer wait to fix problems until layout sign-off, everything has to be done in parallel at each stage.
[Challenges and requirements for 20nm IC design]
As we see, tackling these issues in the design is not enough, the design closer needs to happen in time and with desired PPA in order to avail the window of opportunity in the market. Having earlier worked at Cadence, I can firmly say that this is one company which provides a complete end-to-end solution to the overall design flow, with the whole spectrum of EDA tools for all types of designs; custom, digital, mixed-signal and so on. This company has the right expertise, through its long tenure in semiconductor EDA domain, to address designers’ need at all levels. For example, analog design needs more customized approach whereas digital design has very high level of automation.
[Cadence GigaFlex technology – A flexible modelling approach to manage large designs]
Cadence proposes rapid prototyping and rapid verification methodologies to save significant amount of design time. It uses flexible modelling to support required level of abstraction at each stage. For example, the model at design exploration or planning stage does not require details of that used at block implementation level. Further, it uses an innovative “Prevent, Analyze and Optimize” approach which drives both custom and digital platforms to enable faster design convergence at advanced nodes. In-design sign-off is done at each stage such as placement, routing, lithography analysis, timing and signal integrity and so on by utilizing state-of-the-art sign-off quality tool engines. Also correct-by-construction approach is used at the design time by utilizing smart tools such as constraint-driven design, LDE-aware placement, color-aware P&R and in-design verification.
[Clock Concurrent Optimization combines timing-driven CTS with physical optimization]
Clock Concurrent Design Flow is a paradigm shift that makes Clock Tree Synthesis (CTS) timing window-driven rather than skew-driven, and merges it with physical optimization. This provides significant PPA optimization; 30% saving on power and area and 100MHz of chip performance improvement for a GHz design with ARM processors.
To conclude, there are several challenges to fetch the benefits of 20nm technology, but with right tools, methodologies and collaboration across semiconductor ecosystem, they can easily be achieved. There is a detailed whitepaper from Cadence on the methodologies to be used for 20nm designs, “A Call to Action: How 20nm will Change IC Design”. It’s worth looking at, I enjoyed reading it and jotted down a summary of that in this article. The paper also has other references on 20nm technology. Enjoy reading!!